CLRC66303 Hard Power-Down Consumes ~700 µA on I²C-Only Design (vs 10–30 µA Expected)

[Umasankarc]

Hello,

I am working with the CLRC66303 connected to a TI CC2652R7 MCU over I²C only.
According to the datasheet and the official NXP reference board, the hard power-down current should be around 10–30 µA.

On the official NXP CLRC66303 board, I measure ~30 µA (as expected).

On my custom I²C-only board, I always measure ~700 µA in hard power-down.

Test conditions:

Supply: 3.3 V

Interface: I²C only (SCL, SDA, IRQ with 4.7 kΩ pull-ups)

MCU: TI CC2652R7

PWRDOWN pin controlled correctly by MCU

Firmware sequence is identical to the NXP reference board

Measurement with precision multimeter

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My design (attached schematic):

Based on official NXP CLRC66303 reference

IFSEL0, IFSEL1, IFSEL2 pulled high (4.7 kΩ) → I²C-only mode (address 0x50)

SCL, SDA lines with 4.7 kΩ pull-ups

IRQ line with 4.7 kΩ pull-up

Crystal 27.12 MHz with proper load capacitors

Decoupling capacitors on AVDD, DVDD, TVDD present

SPI pins (NSS, MOSI, MISO, SCK) not connected (floating, since only I²C is used)

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Questions:

1. Is there any predefined NXP firmware step or register setting required before asserting PWRDOWN to achieve the specified 10–30 µA current?

2. For I²C-only designs, are there any hardware or layout changes recommended beyond the reference schematic?

3. Could the unused SPI pins (left floating) be causing leakage in hard power-down? Should they be tied to GND or VCC?

[Fabian_R]

Hello, thank you for your interest in our products.

There isn't any predefined firmware, we recommend please take a look at AN11783, where the specific requirements for achieving a correct LPCD are mentioned.

This requires a Calibration, which we highly recommend to be done using NFC Cockpit.

Additionally, the settings registers and, software handling.

Is possible that these settings aren't correctly configured in your IC and, the CLRC663 is entering into a LPCD mode.

[Fabian_R]

Hello sir,
Regarding question 1, if the state of PDOWN = HIGH the IC will remain in off. This is decribed in section 8.9.2.1 of the Datasheet.
Regarding I2C interface, as mentioned in 8.4.4 there are some important requirements for a successful interfacing but, no specific pin considerations for a proper LPCD state.
LPCD and HDP are two different things. HPD won't automatically detect a card and wake-up the whole system, LPCD will.

Still, if you are using HPD fro manually power down the Reader, the consumption should be very low. There is a chance that you are having issues with Power management in your board design?
What happens if you don't populate the with CLRC663 in your design? Do you get the expected results?
Do you have good results when using the CLRC663 in standby and active state?

[Umasankarc]

Hello Fabian,

Thank you for your response.

I would like to clarify that in my design I am controlling the PDOWN pin directly. According to the datasheet, driving PDOWN = HIGH should place the CLRC66303 into Hard Power-Down (HPD) mode.

However, in my custom design I still observe around 700 µA consumption, while on the official NXP reference board (with the same firmware and MCU) I measure ~30 µA as expected.

To support review, I have attached my firmware code snippet (showing how I control PDOWN) and my schematic design (I²C only).

Could you please confirm:

1. Should PDOWN = HIGH always force the device into Hard Power Down regardless of register settings, or could prior register configuration affect the current level?

2. In an I²C-only design, are there any hardware considerations (pull-ups, unused SPI pins, IRQ, etc.) that could prevent proper HPD current levels?

3. If everything is correct, do you recommend I further test with LPCD instead of relying on HPD for minimum consumption?

Thank you for your guidance.