Hello @db_1008
For trying to investigate the issue you have encountered, I have performed the following steps:
1. Opened the s32k3xx_sil_target_s32ct.slx file, delivered with the toolbox inside the following folder - {toolbox_installation_path}/S32K3_Examples/sil/s32k3xx_simple_s32ct
2. Right clicked the Simulink model canvas and chose Test Harness - Create for Model. In the opened Create Test Harness tab I have completed the Advanced Properties tab with the same settings as the ones you attached inside the SIL_Harness_Creation.png
3. When opening the harness model, and inspecting its properties, I am noticing that the model is created being set for the NXP S32K3xx.
4. Added inputs and outputs inside the harness for performing a SIL simulation
5. Set the Code Interface as Model Reference for the SIL block inside the harness model
6. From the SIL/PIL tab, I am able to successfully run an Automated Verification
Could you please let us know if this is the use case that you are trying to achieve, and check if these steps also work on your setup?
In case you are still encountering issues, could you also please help us with more details so that we could troubleshoot the problem? It would help us to know:
1. Is the model for which you are creating a harness already configured for an S32K3 hardware board?
2. What version of MBDT for S32K3 and MATLAB are you using?
Thank you,
Irina
Hello @Irina_Costachescu
We are following the same above mentioned steps. but getting an error while creating test harness. please find attachment image of the error as well as the model zip file.
the model for which we are creating a harness already configured for an S32K3 hardware board.
The version are :
Matlab Version = R2023b
NXP Toolbox version = Model-Based Design Toolbox for S32K3xx Series Version 1.5.0
Hello @Abhijeet-Starkenn
I have taken a look and tried to create test harnesses for the model attached, and by following the steps mentioned in the previous reply, I was not able to reproduce this error.
However, I have managed to reproduce it by trying to create a Test Harness for the Subsystem placed in your model, instead of creating it for the model itself.
While we furtherly investigate the possibility of creating Test Harnesses for subsystems inside a model, would it be a suitable approach for you to create the Test Harness for the model itself?
Could you please provide more details on the use case that you are trying to achieve so that we could provide more tailored guidance?
For following this proposed workaround (create the Harness for the model), right click on the model canvas and choose Test Harness - Create for Model, as it is described in the Step 2 of the previous reply I have added to this thread.
Please let us know your thoughts on this,
Irina
Could you please proceed with setting
Test Harness -> Create for subsystem -> Advanced properties ->
Verification Mode: Software-in-loop -> Ok.
After this steps, on my system i am getting error "Harness creation Aborted" with error "Error: The model is configured to create a SIL block, which is not supported for the selected hardware board. To resolve this, search for 'Create block' in the Configuration Parameters dialog box and set it to 'None' or 'PIL'."
