SENT Transmitter

[JustMet]

Hello Community,

I use the following code (see the attachment) and made many types of block and configured tlc, the model is always building but I don't see any SENT signal on the oscilloscope 

I took this code and split the main into 2 one driver_setup() -> which contains all setup calls and one driver_action() -> which just contains while call; so that in the tlc file I can call setup only once and wait for trigger in action function.

Second I removed the ADC from the code took ADC config ADC Start from the NXP toolbox and took the data from it to the code same thing but in driver_action() I added a uint32_t Data variable in Parameter -> driver_action(uint32_t Data) and updated the tlc and my model to have one input port. it is built without error but with no result on the oscilloscope.  

also, can I use all flexio pin simuntaniously for SENT Tx for example I use my block multiple times in Simulink and manipulate the data and then pass them to block; will all flexio pin transmit SENT signal w.r.t Data they recieved or is there some trick or something I am missing.

Best regards,
@JustMet 

[JustMet]

Hello

I did some debugging and i found out that when i use clock divider function i see no output and when i disable it i just see clock output and not the SENT also i went a level in and found that selecting SIRC is causing the problem.

void SCG_clock_dividers_setup(void)

{

  SCG->RCCR = SCG_RCCR_SCS(1)     |  /* SCS=2: System Clock Source is SIRC */

              SCG_RCCR_DIVCORE(1) |  /* DIVCORE=1: Divided by 2, thus CORE/SYS_CLK frequency is 8 / 1 = 8MHz */

              SCG_RCCR_DIVBUS(1)  |  /* DIVBUS=1:  Divided by 2, thus BUS_CLK frequency is 8 / 2 = 4MHz */

              SCG_RCCR_DIVSLOW(2);   /* DIVSLOW=2: Divided by 3, thus FLASH_CLK is 8 / 3 = 2.67MHz */

  SCG->RCCR |= SCG_RCCR_SCS(6);      /* SCS=6: System Clock Source is System PLL */

                                     /* DIVCORE=1: Divided by 2, thus CORE/SYS_CLK frequency is 80 / 1 = 80MHz */

                                     /* DIVBUS=1:  Divided by 2, thus BUS_CLK frequency is 80 / 2 = 40MHz */

                                     /* DIVSLOW=2: Divided by 3, thus FLASH_CLK is 80 / 3 = 26.6MHz */

}

Best regards,
JustMet

[JustMet · Accepted solution]

Redefine Divocre Divbuss and Divslow and it work