Hello NXP team,
I am trying to refresh the challenger watchdog of the FS8530 chip during the INIT phase using I2C communication. The problem I am encoutering is that the FS8530 chip power resets every few seconds what probably means that the WD resfresh ends with an error. The FS chip powers the MCU so with every reset the MCU power is also reset.
According to the FS84-85 datasheet, in order to perform a good watchdog refresh the MCU has to send a calculated LFSR value (recieved from the WD_SEED register) to the WD_ANSWER register. The calculation formula is presented in the second picture. In order for the I2C transmit to be valid the MCU has to send a calculated CRC together with the data. The CRC calculation is presented in the third picture.
Even though I believe I've done the steps like described in the datasheet the FS8530 chip power still resets every few seconds. The I2C communication works well, the FS chip sends a seed value (0xAB2) and the MCU sends the calculated value (0xA54D). Is there something missing during the INIT phase for the FS8530 to stop resetting or is the watchdog refresh is performed wrong?
The whole I2C communication process is presented in the first picture.


