Data integrity protection in i.MX RT MBDT

[Maciek]

Hi,

we are in a process of re-designing industrial controller that was developed using an RTOS. To maintain as much compatibility as we can with the previous design - we need to use Simulink messages. The messages are compound objects that use bus objects with enumerations. The message is constructed inside the function-call-subsystem block called by the hardware_interrupt_handler block. The message is then consumed by main application algorithm. This way the message is constructed inside communication peripheral ISR and then consumed inside Timer ISR. I have the following questions:
1. Are there any data integrity protection mechanisms used natively in the generated code ? (I suppose there aren't any...)
2. How can we assure integrity of the compound message (making both interrupts of the same priority can't be done in our application: main algorithm is of lower priority than communication peripheral ISR) ? By using Hardware_Interrupt_Start_Stop block ? Or by writing directly to registers using Write_Register block ?

All these issues were addressed in the previous design using RTOS mutex objects.

Can You comment on that issue ? What are your suggestions ?

Thanks for help
Maciek

[nxa11767 · Accepted solution]

Hi @Maciek ,

I am not aware of a data integrity mechanism to be incorporated default in the generated code.

if you modify/access the compound message in the interrupt routine then the recommended approach is to disable the timer interrupt when entering the interrupt handler do the work and then enable again the interrupts. Here you can either use the Enable/Disable ISR block that will call EnableIRQ/DisableIRQ  or disable/enable the interrupt source of the timer. For the latter we don't have specific blocks in the toolbox, you can either use register block to write the registers that deal with interrupt sources or use custom code block and call the SDK specific functions in the driver:  e.g void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)

Here is also an interesting topic on irq handling: https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-mem...

I hope this helps,

Alexandra

[Maciek]

Thanks @nxa11767 for clear answer and a reference to the article...

Maciek