Nitin
The UARTs are "asynchronous" which means that they 'need' to match the baud rate of the data being received. Also the parity and stop bit settings must match.
The receiver detects a start bit, samples 8 bits of data, the optional parity bit and a number of stop bits. Then it waits for the next start bit.
The Tx generates a start bit (with one Baud period), adds 8 data bits (those received) then adds an optional parity bit, followed by one or two stop bits. Then it is ready to send a following character.
Therefore you have no choice but to set the UART characters accordingly otherwise it will sample in the data content incorrectly and also send it on at a Baud rate that the destination will not understand - On top of that, it its parity setting is wrong the destination may also declare reception as with errors.
In your case what you need is a possibilty to switch the input to the output using a logic circuit and not via UARTs Rx/Tx.
Regards
Mark
This is my scenario:
I am writing SW for the Red font K64F and it is just a bridges between 2 processors.
Initially I thought, I will use DMA with UARTs and it should be done, but it seems from your valid points that it will need me to know the baud rate.
But my problem is, I will NOT know the baud rate, so, I thought let me configure all PINS as MUX 1 so that they act as GPIOs and then via IRQC value of 1 on PORTx_PCRn registers, I can trigger the DMA.
This is the code, I have come up with, but it does NOT work. Thoughts ?
#define SET_PCR_GPIO_ONLY_MASK 0x00000100
#define PIN3_MASK 0x00000008
#define PIN4_MASK 0x00000010
#define PIN6_MASK 0x00000040
#define PIN7_MASK 0x00000080
#define PIN8_MASK 0x00000100
#define PIN9_MASK 0x00000200
#define PIN16_MASK 0x00010000
#define PIN17_MASK 0x00020000
void tScStartup(uint32_t arg1)
{
//UART3 RX
PORTC_PCR16 = SET_PCR_GPIO_ONLY_MASK;
//UART3 TX
PORTC_PCR17 = SET_PCR_GPIO_ONLY_MASK;
GPIOC_PDDR |= PIN17_MASK;
//UART5 RX
PORTE_PCR9 = SET_PCR_GPIO_ONLY_MASK;
//UART5 TX
PORTE_PCR8 = SET_PCR_GPIO_ONLY_MASK;
GPIOE_PDDR |= PIN8_MASK;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
/* trigger DMA on rising edge */
PORTD_PCR6 |= PORT_PCR_IRQC(0x01);
PORTE_PCR9 |= PORT_PCR_IRQC(0x01);
PORTC_PCR3 |= PORT_PCR_IRQC(0x01);
PORTC_PCR16 |= PORT_PCR_IRQC(0x01);
UART3_to_UART5_DMA_init();
UART5_to_UART3_DMA_init();
while(1)
{
_time_delay(10000000);
}
}// end void tScStartup(uint_32 arg1)
void UART3_to_UART5_DMA_init(void)
{
/* Let us DISABLE DMA channel so that we can change the source and then ENABLE it */
DMAMUX_CHCFG2 = 0;
/*Enable DMA MUX ch 0 For DMAMUX channel Cfg Src, Please see Page:94 of USer Manual of K64 here: http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K64P144M120SF5RM.pdf#page=94 */
DMAMUX_CHCFG2 |= DMAMUX_CHCFG_SOURCE(51); //Enable channel 51, Request souurce = PTC16
DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK;
/*** Initialize CH0 -> 1 byte received from UART 0 ***/
/* Set the Source Address*/
DMA_TCD2_SADDR = (uint32_t)(GPIOC_PDIR);
/* Destination address */
DMA_TCD2_DADDR = (uint32_t)(GPIOE_PTOR);
/* Source offset*/
DMA_TCD2_SOFF = 0; // No offset
/*Modulo off and port sizes*/
//DMA_TCD0_ATTR = DMA_ATTR_SSIZE(4) | DMA_ATTR_SMOD(0) | DMA_ATTR_DSIZE(4) | DMA_ATTR_DMOD(0); //16-byte burst
DMA_TCD2_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); //source and destination size 0 = 8 bits
/* Transfer size */
DMA_TCD2_NBYTES_MLNO = 1; //1 byte
/* No adjustment to source address */
DMA_TCD2_SLAST = 0;//-32
/* Destination offset*/
DMA_TCD2_DOFF = 0;
/* No link channel, transactions */
DMA_TCD2_CITER_ELINKNO = 1; //1 major loop
/* Adjustment to destination address */
DMA_TCD2_DLASTSGA = 0;//-32
/* No link channel, transactions */
DMA_TCD2_BITER_ELINKNO = 1; //1 major loop
/*...*/
//DMA_TCD0_CSR = DMA_CSR_DREQ_MASK; //Clear channel's ERQ bit when major loop is complete
DMA_TCD2_CSR = 0; //Never clear channel's ERQ bit
/*Start the sequence*/
DMA_ERQ |= DMA_ERQ_ERQ2_MASK;
}
void UART5_to_UART3_DMA_init(void)
{
/* Let us DISABLE DMA channel so that we can change the source and then ENABLE it */
DMAMUX_CHCFG3 = 0;
/*Enable DMA MUX ch 0 For DMAMUX channel Cfg Src, Please see Page:94 of USer Manual of K64 here: http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K64P144M120SF5RM.pdf#page=94 */
DMAMUX_CHCFG3 |= DMAMUX_CHCFG_SOURCE(53); //Enable channel 11, Request souurce = PortE Pin 9
DMAMUX_CHCFG3 |= DMAMUX_CHCFG_ENBL_MASK;
/*** Initialize CH0 -> 1 byte received from UART 0 ***/
/* Set the Source Address*/
DMA_TCD3_SADDR = (uint32_t)(&GPIOE_PDIR);
/* Destination address */
DMA_TCD3_DADDR = (uint32_t)(&GPIOC_PTOR);
/* Source offset*/
DMA_TCD3_SOFF = 0; // No offset
/*Modulo off and port sizes*/
//DMA_TCD0_ATTR = DMA_ATTR_SSIZE(4) | DMA_ATTR_SMOD(0) | DMA_ATTR_DSIZE(4) | DMA_ATTR_DMOD(0); //16-byte burst
DMA_TCD3_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); //source and destination size 0 = 8 bits
/* Transfer size */
DMA_TCD3_NBYTES_MLNO = 1; //1 byte
/* No adjustment to source address */
DMA_TCD3_SLAST = 0;//-32
/* Destination offset*/
DMA_TCD3_DOFF = 0;
/* No link channel, transactions */
DMA_TCD3_CITER_ELINKNO = 1; //1 major loop
/* Adjustment to destination address */
DMA_TCD3_DLASTSGA = 0;//-32
/* No link channel, transactions */
DMA_TCD3_BITER_ELINKNO = 1; //1 major loop
/*...*/
//DMA_TCD0_CSR = DMA_CSR_DREQ_MASK; //Clear channel's ERQ bit when major loop is complete
DMA_TCD3_CSR = 0; //Never clear channel's ERQ bit
/*Start the sequence*/
DMA_ERQ |= DMA_ERQ_ERQ3_MASK;
}
void UART0_to_UART1_DMA_init(void)
{
/* Let us DISABLE DMA channel so that we can change the source and then ENABLE it */
DMAMUX_CHCFG0 = 0;
/*Enable DMA MUX ch 0 For DMAMUX channel Cfg Src, Please see Page:94 of USer Manual of K64 here: http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K64P144M120SF5RM.pdf#page=94 */
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_SOURCE(52); //Enable channel 52, Request souurce = Port D Pin 6
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;
/*** Initialize CH0 -> 1 byte received from UART 0 ***/
/* Set the Source Address*/
DMA_TCD0_SADDR = (uint32_t)(&PORTD_PCR6);
/* Destination address */
DMA_TCD0_DADDR = (uint32_t)(&PORTC_PCR4);
/* Source offset*/
DMA_TCD0_SOFF = 0; // No offset
/*Modulo off and port sizes*/
DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); //source and destination size 0 = 8 bits
/* Transfer size */
DMA_TCD0_NBYTES_MLNO = 1; //1 byte
/* No adjustment to source address */
DMA_TCD0_SLAST = 0;//-32
/* Destination offset*/
DMA_TCD0_DOFF = 0;
/* No link channel, transactions */
DMA_TCD0_CITER_ELINKNO = 1; //1 major loop
/* Adjustment to destination address */
DMA_TCD0_DLASTSGA = 0;//-32
/* No link channel, transactions */
DMA_TCD0_BITER_ELINKNO = 1; //1 major loop
/*...*/
//DMA_TCD0_CSR = DMA_CSR_DREQ_MASK; //Clear channel's ERQ bit when major loop is complete
DMA_TCD0_CSR = 0; //Never clear channel's ERQ bit
/*Start the sequence*/
DMA_ERQ |= DMA_ERQ_ERQ0_MASK;
}
mjbcswitzerland, after your feedback, this is what I came up with, but still NO data transfer is happening at all:
void UART0_to_UART1_DMA_init(void)
{
/* Let us DISABLE DMA channel so that we can change the source and then ENABLE it */
DMAMUX_CHCFG0 = 0;
/*Enable DMA MUX ch 0 For DMAMUX channel Cfg Src, Please see Page:94 of USer Manual of K64 here: http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K64P144M120SF5RM.pdf#page=94 */
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_SOURCE(52); //Enable channel 52, Request souurce = Port D Pin 6
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;
/*** Initialize CH0 -> 1 byte received from UART 0 ***/
/* Set the Source Address*/
static const unsigned long PTD6 = 0x00000040;
DMA_TCD0_SADDR = (unsigned long)(&PTD6);
/* Destination address */
DMA_TCD0_DADDR = (uint32_t)(&GPIOC_PTOR);
/* Source offset*/
DMA_TCD0_SOFF = 0; // No offset
/*Modulo off and port sizes*/
DMA_TCD0_ATTR = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0); //source and destination size 0 = 8 bits
/* Transfer size */
DMA_TCD0_NBYTES_MLNO = 1; //1 byte
/* No adjustment to source address */
DMA_TCD0_SLAST = 0;//-32
/* Destination offset*/
DMA_TCD0_DOFF = 0;
/* No link channel, transactions */
DMA_TCD0_CITER_ELINKNO = 1; //1 major loop
/* Adjustment to destination address */
DMA_TCD0_DLASTSGA = 0;//-32
/* No link channel, transactions */
DMA_TCD0_BITER_ELINKNO = 1; //1 major loop
/*...*/
//DMA_TCD0_CSR = DMA_CSR_DREQ_MASK; //Clear channel's ERQ bit when major loop is complete
DMA_TCD0_CSR = 0; //Never clear channel's ERQ bit
/*Start the sequence*/
DMA_ERQ |= DMA_ERQ_ERQ0_MASK;
}
This is my DMA register status:
