TWR-K64+TWR-SER+MQX4.1 can it support MII mode? [Branch from: ethernet problem on custom board with MQX 3.8.1]

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TWR-K64+TWR-SER+MQX4.1 can it support MII mode? [Branch from: ethernet problem on custom board with MQX 3.8.1]

1,034 Views
tuowang
Contributor II

Hi Mac,

I have similar questions for MQX 4.1. I am using TWR-K64 + TWR-SER module and by loading the sample code eth_to_ser I am able to ping the MCU (This could verify the jumper settings are correct). I would like to modify BSP project so that I can use MII interface instead of RMII interface. The files I modified are as below:

1.  I changed the parameter in init_enet.c from ENET_OPTION_RMII to ENET_OPTION_MII in ENET_default_params.

2. I added signal assignments in _bsp_enet_io_init in init_gpio.c for MII interface and now it looks like this:

_mqx_int _bsp_enet_io_init

(

    uint32_t device

)

{

    PORT_MemMapPtr pctl;

    SIM_MemMapPtr  sim  = (SIM_MemMapPtr)SIM_BASE_PTR;

    /* TW: modify signal assignments for MII */

    pctl = (PORT_MemMapPtr)PORTA_BASE_PTR;

    pctl->PCR[5]  = 0x00000400;     /* PTA5,  MII0_RXER  */

    pctl->PCR[9]  = 0x00000400;     /* PTA9,  MII0_RXD3  */

    pctl->PCR[10] = 0x00000400;     /* PTA10, MII0_RXD2  */

    pctl->PCR[11] = 0x00000400;     /* PTA11, MII0_RXCLK */ 

    pctl->PCR[12] = 0x00000400;     /* PTA12, RMII0_RXD1/MII0_RXD1      */

    pctl->PCR[13] = 0x00000400;     /* PTA13, RMII0_RXD0/MII0_RXD0      */

    pctl->PCR[14] = 0x00000400;     /* PTA14, RMII0_CRS_DV/MII0_RXDV    */

    pctl->PCR[15] = 0x00000400;     /* PTA15, RMII0_TXEN/MII0_TXEN      */

    pctl->PCR[16] = 0x00000400;     /* PTA16, RMII0_TXD0/MII0_TXD0      */

    pctl->PCR[17] = 0x00000400;     /* PTA17, RMII0_TXD1/MII0_TXD1      */

    pctl->PCR[24] = 0x00000400;     /* PTA24, MII0_TXD2 */

    pctl->PCR[25] = 0x00000400;     /* PTA25, MII0_TXCLK */

    pctl->PCR[26] = 0x00000400;     /* PTA26, MII0_TXD3 */

    pctl->PCR[27] = 0x00000400;     /* PTA27, MII0_CRS  */

    pctl->PCR[28] = 0x00000400;     /* PTA28, MII0_TXER */

    pctl->PCR[29] = 0x00000400;     /* PTA29, MII0_COL  */

  

    pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;

    pctl->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_ODE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO   */

    pctl->PCR[1] = PORT_PCR_MUX(4);                     /* PTB1, RMII0_MDC/MII0_MDC     */

#if ENETCFG_SUPPORT_PTP

    pctl = (PORT_MemMapPtr)PORTC_BASE_PTR;

    pctl->PCR[16+MACNET_PTP_TIMER] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; /* PTC16, ENET0_1588_TMR0   */

#endif

    /* Enable clock for ENET module */

    sim->SCGC2 |= SIM_SCGC2_ENET_MASK;

    return MQX_OK;

}

Then I recompiled and loaded new code to TWR board but it didn't work. I cannot ping the TWR MCU. Can you advise what might be going wrong? I noticed that you mentioned MII clocking is different with RMII. Is there any other BSP files I need to modify or something on my modified code is not correct?

Thank you very much!

Regards,

Tuo

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4 Replies

599 Views
soledad
NXP Employee
NXP Employee

Hello,

In order to change RMII to MII under MQX, you need at minimum:

1. Add the port initialization in init_gpio.c file.

2. Change ENET_OPTION_RMII to ENET_OPTION_MII in ENET_default_params initialization.

3. If you are using different phy change your configuration properly in phy_ksz8041.c

4. Then I think it also changes the way the core clocks are sourced (in RMII they have to be synchronous with PHY, in MII they don’t)

I hope this helps,


Have a great day,
Sol

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599 Views
tuowang
Contributor II

Thanks, Sol,

That's very helpful!

Tuo

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599 Views
macl
Senior Contributor I

Hi,

I am going to branch  this question into a new thread since this is a different topic and different version. I don't personally have experience switching from RMII to MII, but I am sure others do.  You definitely need to make sure that the hardware supports MII.  MII requires more signals to be connected and also the clocking is different.   

Mac

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599 Views
tuowang
Contributor II

Hi Mac,

Yes, the clocking and bootstrapping settings need to change for MII interface:

- MII uses 25MHz clock input so  J2 on TWR-SER sould be set to 1-2.

- No shunt across any pin on J12 of TWR-SER so the PHY KSZ8041NL is bootstrapped for MII interface.

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