SPI chip select offset

[rahuludasi]

I have spi cs 3 enabled using the following code,

spifd = fopen ("spi0:8", NULL);

   if (NULL == spifd) {

      printf ("Error SPI_0:8\n");

   return FALSE;

   }

I then write 0xAA followed by 0x0F,

As can be seen in the image above the data is being read properly by my logic analyzer on the rising edge of the clock but the chip select goes low after the data has been read. If I write more data it just shifts the chip select further to the right. Not sure why this is happening, I have also tried cs 2 with the same result.

Thanks,

Rahul

[RadekS]

Could you please let us know:

1. your version of MQX,
2. which of SPI drivers you use (SPI or SPI_legacy),
3. your board,
4. did you use gpio callbacks for CS signal or CS signal is generated by SPI module (value of BSP_SPI_MEMORY_GPIO_CS)?

I tested SPI1_CS3 at TRW-K60D100M, MQX4.1.1 and everything works correctly.

Have a great day,
RadekS

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[rahuludasi]

I am using MQX version 4.1.1

SPI driver

board is TWR-MCF5225X

I am not using gpio callbacks for CS

My default CS is set to CS 0, MCF5XXX_QSPI_QDR_QSPI_CS0.

Also for some reason CS2 also tends to go low after data transfer. CS0 on the other hand goes low before data transfer, it seems the default CS is not being overridden. If I do a CS with the ioctl call and correct mask the CS changes to CS2 but the other CS0 and CS3 still go low after data transfer.

Thanks,

Rahul

[rahuludasi]

I am installing the drivers with this call,

_mcf5xxx_qspi_polled_install("spi0:", &_bsp_qspi0_init);

Not sure if this is SPI legacy code, the MQX user guide io is a bit vague? Also are the new spi drivers supported on coldfire V2?

Thanks,

Rahul

[RadekS]

Thank you for additional information.

MCF5225X use legacy SPI driver and it seems that CS selection cannot be handled by text parameter (8) in command: spifd = fopen ("spi0:8", NULL);.

Please try edit _bsp_qspi0_init() constant in init_spi0.c file according your needs(CS3).

If you need change CSx during runtime, please use ioctl command IO_IOCTL_SPI_SET_CS.

CS pins are defined as:

#define MCF5XXX_QSPI_QDR_QSPI_CS3                (0x08)

#define MCF5XXX_QSPI_QDR_QSPI_CS2                (0x04)

#define MCF5XXX_QSPI_QDR_QSPI_CS1                (0x02)

#define MCF5XXX_QSPI_QDR_QSPI_CS0                (0x01)

So, if you want CS0 and CS3 signals simultaneously, please use MCF5XXX_QSPI_QDR_QSPI_CS0| MCF5XXX_QSPI_QDR_QSPI_CS3 as parameter for IO_IOCTL_SPI_SET_CS command.

I suppose that chip select offset in your case is just some side effect.

Have a great day,
RadekS

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[rahuludasi]

So does that mean that the new SPI driver is not supported for coldfire or that the coldfire bsp doesnt support the new SPI drivers. If it is the bsp case are they a lot of changes required to get the new SPI drivers working? A brief look at the kinetis code indicated some changes, not sure how much. Also would you knw why all the CS go low for some reason even though they are not used?

Thanks,

Rahul

[RadekS · Accepted solution]

It means that new SPI driver currently support just DSPI module. Unfortunately MCF5225x contains only QSPI module and currently there isn’t any plan for adding QSPI module support into new SPI driver.

So, currently only way is using legacy SPI driver or your own SPI driver (modified or some other SPI driver).

I probably found reason of this behavior – It is exactly according MCF5225x reference manual.

In default state - QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 0, chip selects are active high).

Please check and potentially set CSIV bit in QWR register.

Did you use IO_IOCTL_FLUSH_OUTPUT or  IO_IOCTL_SPI_FLUSH_DEASSERT_CS ioctl commands?