SPI PCS0 not functional on MK20DN512VLK10

[daviduhen]

I am using SPI0 on a MK20DN512VLK10 with MQX 4.0 and having trouble getting anything out of PC0.

_bsp_dspi_io_init has been modified for the pins on PORTA…

        case 0:
            /* Configure GPIOD for SPI0 peripheral function */
            pctl = (PORT_MemMapPtr)PORTA_BASE_PTR;

            pctl->PCR[14] = PORT_PCR_MUX(2);     /* DSPI0.PCS0   */
            pctl->PCR[15] = PORT_PCR_MUX(2);     /* DSPI0.SCK    */
            pctl->PCR[16] = PORT_PCR_MUX(2);     /* DSPI0.SOUT   */
            pctl->PCR[17] = PORT_PCR_MUX(2);     /* DSPI0.SIN    */

            /* Enable clock gate to SPI0 module */
            sim->SCGC6 |= SIM_SCGC6_SPI0_MASK;
            break;

The io channel is initialized and accessed with…

    adc_spi = fopen (ADC_CHANNEL, NULL);
    if (NULL == adc_spi)
        error = TRUE;
    param = 500000;                       // set baud rate
    if (SPI_OK != ioctl (adc_spi, IO_IOCTL_SPI_SET_BAUD, &param))
        error = TRUE;
    param = SPI_CLK_POL_PHA_MODE0;        // set clock mode
    if (SPI_OK != ioctl (adc_spi, IO_IOCTL_SPI_SET_MODE, &param))
        error = TRUE;
    param = SPI_DEVICE_BIG_ENDIAN;        // set endianess 
    if (SPI_OK != ioctl (adc_spi, IO_IOCTL_SPI_SET_ENDIAN, &param))
        error = TRUE;
    param = SPI_DEVICE_MASTER_MODE;       // set transfer mode
    if (SPI_OK != ioctl (adc_spi, IO_IOCTL_SPI_SET_TRANSFER_MODE, &param))
        error = TRUE;
    param = 1;                            // set CS0
    if (SPI_OK != ioctl(adc_spi, IO_IOCTL_SPI_SET_CS, &param))
        error = TRUE;
    if (SPI_OK != ioctl (adc_spi, IO_IOCTL_SPI_READ_WRITE, &adc_rw))

        error = TRUE;

I used the IAR debugger to examine the registers and verified that the PortA PCR[14] through PCR[17] are set correctly with avalue of 0x200.  I also verified that the SPI0 PUSHR has both CONT=1 and PCS=0x01.   The SPI data lines and clock are all working but PORTA[14] just sits there in a high impedance state.  Am I missing a step to enable PCS0 as an output?

[Hab]

Try looking at the SPIx_MCR register - specifically SPI_MCR_PCSIS to enable the specific CS you desire.

Hope this helps.

[daviduhen]

By adding...

      fflush (adc_spi);

before and after the IO_IOCTL_SPI_READ_WRITE call I was able to get the PCS0 line active.

The function fflush() ends up calling _dspi_cs_deassert().  This toggles the MSTR and HALT bits in the SPI_MCR register.

The reference manual describes HALT with "Starts and stops the module transmissions".   It makes sense that this bit has to

be toggled after each transmission.  I'm not sure why MSTR is being toggled or why HALT has to be toggled before PCS0 will

become active for the first time.  Until you call this function the PCS0 line is tri-stated.  That might cause problems for the first

transmission from the SPI.

I guess the moral to the story is like my mom used to say "Always remember to fflush".