Problem with the interrupt priority of the EPORT pin

[elel]

Hi Everybody.

I'm using an MCF52259 with the MQX 3.5.1, and in my application I'm trying to use the pins 1,3, and 5 of the edge port module in way to read a signal provided by an encoder.

My problem is that the interrupt of the pin 3 has a bigger priority respesct the interrupt of the pin 1...but I don't know why.

I've disabled the initalization of the gpio by the mqx (by setting to 0 the define "BSPCFG_ENABLE_GPIODEV" in user_config.h file), and I've initialized the pin in this way:

    //Get the base address
    mcf5225_ptr    =    _PSP_GET_IPSBAR();
    mcf5225_gpio_ptr    =    &mcf5225_ptr->GPIO;
    mcf5225_EPORT_ptr    =    &mcf5225_ptr->EPORT[0];
    

    //Set the pin of the NQ port to work as interrupt pin
    mcf5225_gpio_ptr->PNQPAR    =    (mcf5225_gpio_ptr->PNQPAR | 0x4444);
    //Set the pin of the NQ port to work as input
    mcf5225_gpio_ptr->DDRNQ        =    0x00;
   

    //Set the pin IRQ1,IRQ3, and IRQ5 to generate an interrupt on both, rising and falling, edge
    mcf5225_EPORT_ptr->EPPAR    |=    0x00CC;

    //Set the pin IRQ1,IRQ3, and IRQ5 to work as input
    mcf5225_EPORT_ptr->EPDDR    &=    ~0x2A;

    //Enable the interrupt generation for pin IRQ1 and IRQ3

    //the IRQ5 interrupt it's enabled later...
    mcf5225_EPORT_ptr->EPIER    |=  0x0A;

   //Set the irq function for IRQ1 pin interrupt  

       if(_int_install_isr(MCF5225_INT_EPORT0_EPF1, Encoder_Channel_A_ISR, NULL)==NULL)
       {
           return ERROR_INIT_IRQ_1;
       }
       
   //Set the irq function for IRQ3 pin interrupt
       if(_int_install_isr(MCF5225_INT_EPORT0_EPF3, Encoder_Channel_B_ISR, NULL)==NULL)
       {
           return ERROR_INIT_IRQ_3;
       }
       
   //Set the irq function for IRQ5 pin interrupt
       if(_int_install_isr(MCF5225_INT_EPORT0_EPF5, Encoder_Channel_Z_ISR, NULL)==NULL)
       {
           return ERROR_INIT_IRQ_5;
       }

     //Unmask the IRQ1,IRQ3, and IRQ5 interrupt
       _mcf5225_int_unmask(MCF5225_INT_EPORT0_EPF1);
       _mcf5225_int_unmask(MCF5225_INT_EPORT0_EPF3);
       _mcf5225_int_unmask(MCF5225_INT_EPORT0_EPF5);

I have not set the level and the priority of this interrupt because in the "reference manuale" it's write that for the IRQ pin the level and the priority are set by the hardware(it's correct?).

How can I fix this problem?

Stefano

[JuroV · Accepted solution]

Hi Stefano.

Interrupt levels for IRQ are indeed set by hardware, but for pin #1 the level is #1, for pin #3 the level is #3 etc. It means that they dont have the same level.

[elel]

Thanks Juro V.

After your explanation I've read again the "interrupt controller" chapter in the reference manual and now I've understand.

I was wrong because I've thinked that the "midpoint level priority" described in the manual was for level and for priority too, instead it's only for the level, and inside that level each pin has it's own priority from 1 to 7...

Stefano

[elel]

Hi Everybody.

I've another problem with the EPORT pin interrupt.

In my application I use 4 interrupt sources: the pit0 interrupt, the pit1 interrupt(used by the mqx's adc driver), the irq1 interrupt, and the irq3 interrupt.

The irq1, and irq3, pins are connected to the signals "A" and "B "of an encoder.

I've setted the irq1 and irq3 for sampling rising edge, and into the isr that I wrote for this 2 interrupt I toggle the state of 2 gpio configured as output.

Then I've monitored the signals with an oscilloscope, and I've saw that: the irq3 isr is serviced 4 microseconds after the pin has captured the rising edge, instead the irq1 isr is serviced after a few,and not repetitive, microseconds(sometimes 6, sometimes 10,sometimes 30...).

After some tests I've understood that the irq1 isr is serviced only after the pit0(or pit1) isr is been serviced.

So I've modified the level of pit0 interrupt and pit1 interrupt in way to set those level lower than the mid-point priority level of the EPORT pin interrupt.

But the problem remains the same.

I can see the irq1 interrupt working correctly only if I disable the pit0 and pit1 interrupt.

Any ideas on why this problem appens? am I doing something wrong?

Thanks in advace.

Stefano

P.s. I've bypassed the problem by connecting the signal "A" of the encoder(originally connected on the EPORT pin1) on the EPORT pin 5... in this way I can see my application working good.

[JuroV]

Hi elel,

Freescale User Manual is a bit confusing concerning interrupts. Interrupt controller has 2 stages of priorities:

1) interrupt level

2) interrupt priority, or sublevel, or priority within level

The most important value do decide if interrupt is masked or not is the interrupt level. This is in EPORT wired for IRQ3 to level 3, for IRQ5 to level 5.

Every interrupt request has its own subpriority, i.e. priority within level. It can be programmed, but for IRQ (EPORT) interrupt, this is also hard-wired to the middle and is supposed to be considered as 3.5 (three and half).

To sum it up, IRQ5 has higher priority than IRQ3, as IRQ5 runs at level 5 and IRQ3 runs at level 3. Interrupt priority within level is considered when 2 request with the same level are invoked: the one with higher priority within level will be acknowledged by interrupt controller.

[elel]

Hi Juro V.

What I don't understand is the reason why pit0 interrupt, and pit1 interrupt, are more prioritary than irq1 interrupt, since I've setted the level of pit0,and pit1, interrupt at 2.

So if the level of the EPORT pin is the middlepoint between 3 and 4, the level 2 is less prioritary respect the irq1 interrupt level.

But, in my tests, I've saw that the irq1 interrupt is served only when pit0 and pit1 are not served.

Stefano

[JuroV]

"So if the level of the EPORT pin is the middlepoint between 3 and 4..."

False. The level of the EPORT pin is #1 for IRQ1, as I wrote. Is level #1 less than level #2 (level of your PIT timer)? Yes. What does it mean then? PIT timer interrupt is served prior to IRQ1.

[elel]

Hi Juro V.

Now I've understand... I've made confusion between the words "level" and "priority".
I had understood that, for the EPORT pin, the level is the "middle point", and the priority is established by the pin's ID; instead  the level is established by the pin's ID and the priority is the "middle point"... is correct?

Sorry for the misunderstanding.

Stefano

[JuroV]

As I wrote above, it is confusing, that's why I explained in my second post in this thread how it is in fact. Now, you are correct.