Periodic Timers - Help?

[OldNick]

Does anybody know how to get the peridic timers up on a Kinetis in MQX 370?

I've got th eregisters configures, and followed the ISR example to chain an interrupt handler.

The counter counts down, the interrupt bit gets set, but the ISR is not being called.

Not sure I want to install a kernel interrupt if the vectors might be/are in ROM

:?

[OldNick]

OK...so there is a feature beautifully hidden across two websites and four different sources of documentation, called _bsp_init_interrupt, which sets up the NVIC for my timer.

Spent a happy morning attaching the ISR to a GPIO pin on my target, and hoped to see a regular toggle of the GPIO pin.

Nope.

The first time I run the target (under J-link) the pin gets toggled, then stays high.  If I break the execution, then continue it, the pin gets toggled low, then stays that way.  etc. etc.

Every time I break and continue, the pin gets toggled. 

Once

.

[tr9]

I experienced the same problem.

Try reading either the CLVAL or LDVAL register in your PIT interrupt handler. I think that will solve your problem. You don't have to do anything with the value, just read the register.

This behavior does not appear to be documented, . . .  maybe it wasn't intentional. In any case, after reading CVAL upon a PIT interrupt, you should get repeated PIT interrupts. I have forwarded this problem to Freescale and they are looking at it.

Let me know if this works for you.

[OldNick]

Thanks, but see my last post.

Kinetis early silicon - errata. 

Read CVAL in the interrupt handler and it works. 

Just like you said.

[OldNick · Accepted solution]

B

E

A

youtiful...

From the Kinetis Errata for OM33Z

e2682: PIT: Does not generate a subsequent interrupt after clearing the interrupt flag
Errata type: Errata
Description: The PIT does not generate a subsequent interrupt after clearing the interrupt flag in the ISR
upon receiving the first interrupt. Thus, the second interrupt will never be triggered.
Workaround: In order to enable the use of subsequent interrupts from the PIT, the user must access any PIT
register after clearing the interrupt flag in the ISR.

Turns out that because I had the memory window open on the registers, every time I stopped the debugger I was clearing the error by accident.

Put in a read of PIT_CVAL at the bottom of the interrupt handler and all is well