Number of K24 interrupt priorities?

[fcw]

I'm chasing down what appears to be screwball interrupt responses. Section 3.2.2.1 of the K24 reference manual states the chip has 16 interrupt priority levels. The MQX PSP cortex.h header states  "#define CORTEX_PRIOR_IMPL  (3) " which is manipulated into a left-justified 3-bit mask as required for the NVIC.

- Does the chip have 8 or 16 levels?

- If 16, is the use of 8 by MQX intentional?

[fcw]

Got it. Thank you!

[danielchen · Accepted solution]

Hi FRED WEDEMEIER

On Cortex-M4 and Cortex-M5 core based platforms, the MQX RTOS interrupt processing is designed this way.

Kinetis K family MCUs support 16 hardware interrupt priority levels. Internally MQX RTOS maps even levels (0,2,4,...,14) for MQX RTOS applications while odd levels (1,3,5,...15) are used internally.

MQX RTOS application interrupt levels are 0 to 7, the mapping from MQX RTOS application levels 0 to 7 to hardware priority levels (0, 2, ..., 14) is implemented in the _bsp_int_init() function.

Have a great day,
Daniel

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