MQX4.1 on k20d50m I2C0 pin mux

[huishao2]

Hi-

In k20d50m BSP for MQX4.1, the I2C0 pin config is done as below in init_gpio.c. There pctl->PCR[2] and pctl->PCR[3] are used to configure SCL and SDA for I2C0. It looks like it uses pin PTB2 and PTB3 instead of PTB0 and PTB1 as stated in K20P32M50SF0RM shown as snapshot below.

So question is, which PTB pins are correct?

_mqx_int _bsp_i2c_io_init
(
    uint32_t dev_num
)
{
    #define ALT2 0x2

    PORT_MemMapPtr  pctl;
    SIM_MemMapPtr sim = SIM_BASE_PTR;

    switch (dev_num)
    {
        case 0:
            pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;

            pctl->PCR[2] = PORT_PCR_MUX(ALT2) | PORT_PCR_ODE_MASK;  /* I2C0.SCL */
            pctl->PCR[3] = PORT_PCR_MUX(ALT2) | PORT_PCR_ODE_MASK;  /* I2C0.SDA */
            /* Enable SDA rising edge detection */
#if BSPCFG_ENABLE_LEGACY_II2C_SLAVE
            pctl->PCR[3] |= PORT_PCR_IRQC(0x09);
            pctl->PCR[3] |= PORT_PCR_ISF_MASK;
#endif
            sim->SCGC4 |= SIM_SCGC4_I2C0_MASK;

            break;

        default:
            /* Do nothing if bad dev_num was selected */
            return -1;
    }

    return MQX_OK;

}

[danielchen]

Hi Hui

Please refer to K20P64M50SF0, PTB2/PTB3 is right, PTB0/PTB1 also right. K20P64 is on K20D50M

Have a great day,
Daniel

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[huishao2]

Hi Daniel

Looks like we are not using same document. I am using the one for MK20DX128VFM5 that doesn't have PTB2 and PTB3. So I assume this is a bug I need modify the code in _mqx_int _bsp_i2c_io_init() for this model.

Thanks!

Hui

[danielchen · Accepted solution]

K20D50m BSP is for TWR-K20D50M board, if you are using other MCU,  you need to modify the BSP according to your requirements