Hi Louie:
Please check my modifications based on BSP_twrk70, I use PTE4/5 as the rx/tx pin according to your requirement
I enabled ttyd in user_config.h
and modify the _bsp_serial_io_init function in init_gpio.c
case 3:
pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;
if (flags & IO_PERIPHERAL_PIN_MUX_ENABLE)
{
/* PTE5 as RX function (Alt.3) + drive strength */
pctl->PCR[5] = 0 | PORT_PCR_MUX(3) | PORT_PCR_DSE_MASK;
/* PTE4 as TX function (Alt.3) + drive strength */
pctl->PCR[4] = 0 | PORT_PCR_MUX(3) | PORT_PCR_DSE_MASK;
}
if (flags & IO_PERIPHERAL_PIN_MUX_DISABLE)
{
/* PTE5 default */
pctl->PCR[5] = 0;
/* PTE4 default */
pctl->PCR[4] = 0;
// /* default */
}
if (flags & IO_PERIPHERAL_CLOCK_ENABLE)
{
/* start SGI clock */
sim->SCGC4 |= SIM_SCGC4_UART3_MASK;
}
if (flags & IO_PERIPHERAL_CLOCK_DISABLE)
{
/* stop SGI clock */
sim->SCGC4 &= (~ SIM_SCGC4_UART3_MASK);
}
break;
then rebuild bsp and psp, debug, I can see the PTE4/5 setting is as below, please check whether it can work on your side or not.

Regards
Daniel
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