I2S/SAI audio clock control in MQX

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I2S/SAI audio clock control in MQX

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eddiec
Contributor II

Hi All,

I build an platform by using TWR-K60F120M(Rev.C ) with my own CODEC board, connected with wire from TWR's female header A21~A25( I2S signal and clock), my system are CW10.5 and MQX4.0.0.

I tested the "i2s_demo" under "mqx" subfolder, insert a microSD card including a 48kHz/24bit stereo wav file then download the project. when I type play command on shell, I can see the wav file is playing well on console( there are some error message stop on "initial_codec" and "setup_codec", so I commented them out to pass it), but the clock signal are not correct. so I change "CLK_MULT" from 384 to 256 then I could measure that MCLK = 12.288MHz and BCLK = 3.072MHz( system use EXTAL_MAIN 50MHZ by default, jumper J18 on and J6 off), that's what I need but LRCK is 64kHz, it's very weird because I had checked the wav file header and played by some audio player, the sample rate is 48kHz, but sample rate on shell message is 51200Hz, and 64000Hz on LRCK pin as I mentioned earlier.


When I played a sound file A.wav(48kHz/16bit-stereo), the I2S clock are MCLK = 12.288MHz' SCLK = 1.536MHz' LRCK = 48kHz, and playback information on shell displays 48000Hz, it plays no problem; but when I play a sound file B.wav(48kHz/24bit-stereo), the I2S clock are MCLK = 12.288MHz' SCLK = 3.072MHz' LRCK = 64kHz, and playback information on shell displays 51200Hz, it's very strange because 1536/48 is not equal to 3072/64, It's hard to realize how system can get these value, especially 51200 on shell.


And Finally I found LRCK is controlled by 4 parameters: SYWD in TCR4, WNW' W0W and FBT in TCR5, but it's hard to understand how it works.


Is there anybody know how to control LRCK? 48kHz/24bit format is the only one I use!

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soledad
NXP Employee
NXP Employee

Hi,

You can try using Processor Expert please check the attached document, you can use this document like a guide in order to change the clock configurations.

Have a great day!!

Regards

Sol

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eddiec
Contributor II

Hello! soledad,

Thanks for your reply!

My problem is how to control LRCK and BCLK, then let I2S system can work correctly with 24 sample bit. The document is talking about system clock, but my system clock is correct(12.288MHz), so I think it's not helpful to the problem. :smileysad:

Best regards

Eddie

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