How to change SPI0 pins on MQX 4.1 for a TWRK64

[julxhinogocllar]

Hello,

I've been using a K64 Tower Board with CW 10.6 and MQX 4.1.  Please bare with me as I try to explain what I'm trying to accomplish.

1.  The MQX 4.1 SPI driver has    "SPI0_SIN" on PTD3   /     "SPI0_SOUT" on PTD2      /  "SPI0_SCK" on PTD1   , (I have verified this stuff with a scope using a provided example project)

2.  According to the data sheet of the K64, SPI0_SIN/SPI0_SOUT/SPI0_SCK   can be "routed" to different pins, for example SPI0_SIN can also be "routed" to PTA17, PTC7 (in addition to PTD3 (which is the default)) 

3.  MY QUESTION IS:     How can I change the default "pin mapping" ?  For example how can I make SPI0_SIN be "routed" to PTA17 as opposed to PTD3 ?

Thank you for your time and help in advance,

Gino

[louiemoye]

Hello - What do the numbers represent (4,5,17,17) ?

Thanks,

Louie

#define BSP_DSPI2_DMA_RX_CHANNEL        (4)

#define BSP_DSPI2_DMA_TX_CHANNEL        (5)

#define BSP_DSPI2_DMA_RX_SOURCE        (17)

#define BSP_DSPI2_DMA_TX_SOURCE        (17)

[soledad · Accepted solution]

Hi,

You need to modify three files:

1. User_config.h : This is in order to enable the SPI driver

#define BSPCFG_ENABLE_SPI0 1

    2. twrk64f120m.h : You need to modify the below parameters according your needs

/*-----------------------------------------------------------------------------

**                      DSPI

*/

#define BSP_DSPI_INT_LEVEL              (4)

#define BSP_SPI_MEMORY_CHANNEL          (0)

#define BSP_DSPI0_DMA_RX_CHANNEL        (0)

#define BSP_DSPI0_DMA_TX_CHANNEL        (1)

#define BSP_DSPI0_DMA_RX_SOURCE        (14)

#define BSP_DSPI0_DMA_TX_SOURCE        (15)

#define BSP_DSPI1_DMA_RX_CHANNEL        (2)

#define BSP_DSPI1_DMA_TX_CHANNEL        (3)

#define BSP_DSPI1_DMA_RX_SOURCE        (16)

#define BSP_DSPI1_DMA_TX_SOURCE        (16)

#define BSP_DSPI2_DMA_RX_CHANNEL        (4)

#define BSP_DSPI2_DMA_TX_CHANNEL        (5)

#define BSP_DSPI2_DMA_RX_SOURCE        (17)

#define BSP_DSPI2_DMA_TX_SOURCE        (17)

     3. init_gpio.h : Also you need to modify the below parameters according your needs

/*FUNCTION*-------------------------------------------------------------------

*

* Function Name    : _bsp_dspi_io_init

* Returned Value  : MQX_OK or -1

* Comments        :

* This function performs BSP-specific initialization related to DSPI

*

*END*----------------------------------------------------------------------*/

_mqx_int _bsp_dspi_io_init

(

uint32_t dev_num

)

{

SIM_MemMapPtr  sim = SIM_BASE_PTR;

PORT_MemMapPtr  pctl;

switch (dev_num)

{

case 0:

            /* Configure GPIOE for DSPI0 peripheral function */

            pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;

            pctl->PCR[16] = PORT_PCR_MUX(2);    /* DSPI0.PCS0  */

            pctl->PCR[17] = PORT_PCR_MUX(2);    /* DSPI0.SCK    */

            pctl->PCR[18] = PORT_PCR_MUX(2);    /* DSPI0.SOUT  */

            pctl->PCR[19] = PORT_PCR_MUX(2);    /* DSPI0.SIN */

            /* Enable clock gate to DSPI0 module */

            sim->SCGC6 |= SIM_SCGC6_DSPI0_MASK;

            break;

case 1:

            /* Configure GPIOE for DSPI1 peripheral function    */

            pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;

            pctl->PCR[1] = PORT_PCR_MUX(2);    /* DSPI1.SOUT  */

            pctl->PCR[2] = PORT_PCR_MUX(2);    /* DSPI1.SCK    */

            pctl->PCR[3] = PORT_PCR_MUX(2);    /* DSPI1.SIN */

            pctl->PCR[4] = PORT_PCR_MUX(2);    /* DSPI1.PCS0  */

            /* Enable clock gate to DSPI1 module */

            sim->SCGC6 |= SIM_SCGC6_DSPI1_MASK;

            break;

case 2:

            /* Configure GPIOD for DSPI2 peripheral function    */

            pctl = (PORT_MemMapPtr)PORTD_BASE_PTR;

            pctl->PCR[11] = PORT_PCR_MUX(2);    /* DSPI2.PCS0  */

            pctl->PCR[12] = PORT_PCR_MUX(2);    /* DSPI2.SCK    */

            pctl->PCR[13] = PORT_PCR_MUX(2);    /* DSPI2.SOUT  */

            pctl->PCR[14] = PORT_PCR_MUX(2);    /* DSPI2.SIN */

            pctl->PCR[15] = PORT_PCR_MUX(2);    /* DSPI2.PCS1  */

            /* Enable clock gate to DSPI2 module */

            sim->SCGC3 |= SIM_SCGC3_DSPI2_MASK;

            break;

default:

            /* do nothing if bad dev_num was selected */

            return -1;

}

return MQX_OK;

}

You can find these files at the path C:\Freescale\Freescale_MQX_4_1\mqx\source\bsp\twrk64f120m

Don’t forget to rebuild the libraries after these modifications.

Have a great day,
Sol

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[julxhinogocllar]

Thank you, that worked