Could you confirm if this is a bug or a feature in MQX 4.1?

[m4l490n]

There is a part in the file cortex.h that is as follows:

/* minimal implemented priority required by Cortex core */

#ifndef CORTEX_PRIOR_IMPL

    #if PSP_MQX_CPU_IS_ARM_CORTEX_M0P

        #define CORTEX_PRIOR_IMPL (1)

    #elif PSP_MQX_CPU_IS_ARM_CORTEX_M4

        #define CORTEX_PRIOR_IMPL (3)

    #endif

#endif /* CORTEX_PRIOR_IMPL */

The CORTEX_PRIOR_IMPL value is used to set the value of the priority levels in nvic.c (line 58, fcn _nvic_int_init), and that definition is saying that for Cortex M4 the CORTEX_PRIOR_IMPL is 3 but that seems to be wrong. Reading on the reference manual for the MCU family I'm using it says that it supports up to 16 priority levels. Having that definition as 3 limits the priority levels to 8 and that is just half of what we would have available.

I don't remember having read anything about cortex.h being a file that can be configured by the user but if I change that 3 for a 4 then I have all 16 priority levels available.

It seems like that value as 3 could be the correct value for some families with less than 16 priority levels and that for other families like the one I'm using it can be configured as 4, but I'm not sure.

Is this a bug or something that is supposed to be that way? Could someone please confirm this?

[danielchen · Accepted solution]

Hi Manuel:

On Cortex-M4 and Cortex-M5 core based platforms, the MQX RTOS interrupt processing is designed this way.

Kinetis K family MCUs support 16 hardware interrupt priority levels. Internally MQX RTOS maps even levels (0,2,4,...,14) for MQX RTOS applications while odd levels (1,3,5,...15) are used internally.

MQX RTOS application interrupt levels are 0 to 7, the mapping from MQX RTOS application levels 0 to 7 to hardware priority levels (0, 2, ..., 14) is implemented in the _bsp_int_init() function.

Have a great day,
Daniel