Hi All,
I am using TWRK60N512 and MQX 3.8. I am using KSZ8895MQ with MII Interface on my custom board. I know there are issues, such that TWRK60N512 cannot be used in MII mode (as some of the pins are use for JTAG) but I will be trying this on custom board.
I want to know what are the changes required in the MQX code for TWRK60N512 in order to convert from RMII to MII Interface. Do we only require seting the required pins within init_gpio.c and selecting ENET_OPTION_MII option or are there any other modifications needed ?
Thanks,
Mohsin
Hi All,
Can anyone please provide the steps required to change from RMII to MII?
Thanks,
Mohsin
https://community.freescale.com/thread/102212
This thread covers some of the difficulties in detail. I hope it helps. In short, it sounds like it is not possible using the TWR peripherals unless I'm missing something.
Hi,
I know the issues when using MII with TWRK60N512. I just wanted to know what steps are required in order to use it on my custom board.
I have made the following changes.
1) Added the port initialisation in init_gpio.c file.
2) Changes ENET_OPTION_RMII to ENET_OPTION_MII in ENET_default_params initialisation.
3) Changed the MII register defines as the were a bit different but still using similar function as in phy_ksz8041.c
Are there any other changes required ?
thanks,
Mohsin
We are using TWRK60F and MQX 4.0 besides KSZ8041NL with RMII Interface on my custom board. I discovered a problem because RMII_MDC does not show any signal.
I am using original driver, I saw a detail about your problem, interesting for me, maybe your answer could helpme to resolve my problem.
what do you do here?
1) Added the port initialisation in init_gpio.c file.
Aditional question: Do you have idea about what is the source of RMII_MDC?
Thanks a lot in advance for your help
No, these steps should work !
Maybe some hardware problems? My problem was i connected the MII0_RXER pin to the PHY ..
Disconnected this pin .. its not requiered
Just edit the init_gpio.c ..
should look like this:
#if 0 // tower .. pctl->PCR[12] = 0x00000400; /* PTA12, RMII0_RXD1/MII0_RXD1 */ pctl->PCR[13] = 0x00000400; /* PTA13, RMII0_RXD0/MII0_RXD0 */ pctl->PCR[14] = 0x00000400; /* PTA14, RMII0_CRS_DV/MII0_RXDV */ pctl->PCR[15] = 0x00000400; /* PTA15, RMII0_TXEN/MII0_TXEN */ pctl->PCR[16] = 0x00000400; /* PTA16, RMII0_TXD0/MII0_TXD0 */ pctl->PCR[17] = 0x00000400; /* PTA17, RMII0_TXD1/MII0_TXD1 */#else pctl->PCR[14] = PORT_PCR_MUX(4);//RMII0_CRS_DV/MII0_RXDV // disconnect this pin if you have connected it to the PHY .. ! //pctl->PCR[5] = PORT_PCR_MUX(4);//RMII0_RXER/MII0_RXER pctl->PCR[12] = PORT_PCR_MUX(4);//RMII0_RXD1/MII0_RXD1 pctl->PCR[13] = PORT_PCR_MUX(4);//RMII0_RXD0/MII0_RXD0 pctl->PCR[15] = PORT_PCR_MUX(4);//RMII0_TXEN/MII0_TXEN pctl->PCR[16] = PORT_PCR_MUX(4);//RMII0_TXD0/MII0_TXD0 pctl->PCR[17] = PORT_PCR_MUX(4);//RMII0_TXD1/MII0_TXD1 pctl->PCR[11] = PORT_PCR_MUX(4);//MII0_RXCLK pctl->PCR[25] = PORT_PCR_MUX(4);//MII0_TXCLK pctl->PCR[9] = PORT_PCR_MUX(4);//MII0_RXD3 pctl->PCR[10] = PORT_PCR_MUX(4);//MII0_RXD2 pctl->PCR[28] = PORT_PCR_MUX(4);//MII0_TXER pctl->PCR[24] = PORT_PCR_MUX(4);//MII0_TXD2 pctl->PCR[26] = PORT_PCR_MUX(4);//MII0_TXD3 pctl->PCR[27] = PORT_PCR_MUX(4);//MII0_CRS pctl->PCR[29] = PORT_PCR_MUX(4);//MII0_COL#endif pctl = (PORT_MemMapPtr)PORTB_BASE_PTR; pctl->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_ODE_MASK; /* PTB0, RMII0_MDIO/MII0_MDIO */ pctl->PCR[1] = PORT_PCR_MUX(4); /* PTB1, RMII0_MDC/MII0_MDC */
And edit the init_enet.c
shoud look like this:
const ENET_PARAM_STRUCT ENET_default_params[BSP_ENET_DEVICE_COUNT] = { { &ENET_0, Auto_Negotiate,#if 0 // tower .. ENET_OPTION_RMII |#endif ENET_OPTION_PTP_MASTER_CLK, BSPCFG_TX_RING_LEN, // # tx ring entries BSPCFG_TX_RING_LEN, // # large tx packets ENET_FRAMESIZE, // tx packet size BSPCFG_RX_RING_LEN, // # rx ring entries BSPCFG_RX_RING_LEN, // # normal rx packets - must be >= rx ring entries ENET_FRAMESIZE, // ENET_FRAMESIZE, // rx packet size BSPCFG_RX_RING_LEN, // # rx PCBs - should be >= large rx packets. 0, 0 },};
that's all for me