on chip DMA of MPC5777C

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on chip DMA of MPC5777C

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prasad1
Contributor I

I am using on chip DMA of MPC5777C for data transfer from flash to RAM. Can Core and DMA access same ram memory address for read/write at the same time? If yes, then can you explain what will happen in following scenarios?

  1. Core is reading ram address and DMA is writing that address at the same time
  2. Core is writing ram address and DMA is reading that address at the same time
  3. Core and DMA is reading that address at the same time
  4. Core  and DMA is writing that address at the same time

Can you please explain crossbar switch significance in this case?

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, in this case it is just given by priority setting for particular XBAR slave (in your example internal SRAM i.e. ports 2 and 4). It does not matter if the access is read or write, it occupies the same bus.

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prasad1
Contributor I

Hi David,

Thanks for your quick reply. Does it mean that core can't access peripheral bus while edma transfer is going on? (Core will do some other work which is independent of peripheral bus or will wait for return of peripheral bus control till edma is transfer is going on.)

Thanks in advance. 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Two masters cannot access one slave at the same time (for instance eDMA and Core both wanting to access PRAMC_0). Two masters can access two different slaves simultaneously.

One yet note that PRAMC has two ports split according address into two halves. Thus two SRAM accesses may run in parallel if both belong to opposite SRAM portion.

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