how to configure adc_pal to for multi-channel AD conversion for MPC5777C?

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how to configure adc_pal to for multi-channel AD conversion for MPC5777C?

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LyncLin
Contributor II

I want to use a 100 us periodic hardware trigger to start a ADC group conversion with DMA. In my case, there are 6 ADC channels in the queue for a single convesion. However, only 4 entries are avaiable in CFIFO/RFIFO according to the RM, so overflow of FIFO will occur and block the next conversion. What should I do if I want to make a single continous conversion with more than 4 channels?

Another question is what's the maxium clock of ADC module for mpc5777c? I use directly the system clock (100 Mhz) without scaling, it it seems the ADC module can success to convert. What's the impact if I use an excessive ADC clock?

Thanks for your kind reply.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

1) It is a bit otherwise. CFIFO has depth of 4 entries, but Cqueue can have any length because commands are continuously filled by DMA.

davidtosenovjan_1-1638976667057.png

Special case is using of streaming mode that can be typically used without DMA for command filling as they can be locked in CFIFO, but in this case CFIFO can be lengthened to 8 entries.

Typical issue that can lead in eQADC command underflow or result overflow is heavy loaded transfers over XBAR ports (typically SRAM and PBRIDGE where eQADC resides). Of course, if DMA is configured properly. It is needed to utilize cross-bar switch advantages and set higher priority for DMA than CPU.

 

2) ADC clock is 33MHz at most. In case you are using higher frequency, module may not work properly and ADC specification is not met. It is use out of specification.

 

 

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LyncLin
Contributor II

Hi,

Thanks for your reply.

Does it mean the DMA fill the CFIFO too fast that reults in the over-folw since EQADC don't have enough time to excute the sampling?

If the I decrease the clock of DMA to slow down the rate it fills the CFIFO, I can have a Cqueue legnth larger than 4?

regards,

Lync

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