how could I efficiently use the 64 MB for MPC5604

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how could I efficiently use the 64 MB for MPC5604

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Learner123
Contributor II

MPC 5604 for can 1 , I have 64 MB ,everytime I only use 1 MB to receive message from CAN receive interrupt;how could I efficiently use the 64 MB,I mean how could I use 2 or more MBs to receive message,the document only tells use 1 MB to do the work,

thanks in advance

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

obviously more RX MBs are used if receiving different IDs, each MB receive its own message. Also you can receive messages for some ID range into single message configuring mask registers accordingly. If you are receiving single ID you can use just single MB and read it each time message comes. But you can also prepare more MBs for the same ID and create so called RX queue, so you would not need to read MBs so often. Refer to chapters Receive and Matching process of the RM for more info.

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

obviously more RX MBs are used if receiving different IDs, each MB receive its own message. Also you can receive messages for some ID range into single message configuring mask registers accordingly. If you are receiving single ID you can use just single MB and read it each time message comes. But you can also prepare more MBs for the same ID and create so called RX queue, so you would not need to read MBs so often. Refer to chapters Receive and Matching process of the RM for more info.

BR, Petr

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Learner123
Contributor II

Hi

The document you offered last time don't have the chapters 'Receive and Matching process of the RM', could you provide another document to me?

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

there is no special document for this. I meant chapters in device Reference Manual, general description for receive and matching process.

BR, Petr

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1,541 Views
Learner123
Contributor II

Hi

I have searched some documents about how to use MB,but i still have question

1: if i use RX FIFO mode,for CAN 1, Are we have 16 FIFOs and 56 MBs? and we can use 72 ID to filter message? 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

on MPC5604 the RXFIFO structure is 

PetrS_0-1631595818249.png

the memory area from 0x80 to 0xFF (which is normally occupied by MBs 0 to 7) is used by the reception FIFO engine. MB0 is the port through which the CPU reads data from the FIFO (the oldest frame received and not read yet). The region 0x90–0xDF (MB1-MB5) is reserved for internal use of
the FIFO engine. The region 0xE0–0xFF (MB6-MB7) contains an 8-entry ID table that specifies filtering criteria for accepting frames into the FIFO.

So if RXFIFO is enabled MB8-MB63 can be used as TX or RX MBs.

BR, Petr

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