eQADC with eDMA don't work well... (@MPC5644A)

[najongmin]

My System

1. OS : OSEK

2. Debugger : TRACE32

3. Compiler : Wind River 5.9.4

4. IDE : Eclipse Luna

Hi,

Today I fell in incomprehensible problem.

I using eDMA for getting eQADC value.

For example..

ISR(GFR_EMIOS_23)

{

      Interrupt flag clear

      eDMA ch01 Enable

      eDMA ch02 Enable

     cFIFO SW Tringger

}

Next...

ISR(INTL_EMDA_01??)

{

      Interrupt flag clear

      my value = rQueue0[0];

}      

eDMA set through the RAppID.

so It is work well... until yesterday.

but.. when I added some function at ISR(INTL_EMDA_01??)..

namely,

ISR(INTL_EMDA_01??)

{

      Interrupt flag clear

      my value = rQueue0[0]

      my_added_function( ) : purpose = local variables copy to global variables(use memcpy)

}

The problem is occuring.

as you know, cFIFO and rFIFO are 1:1 matching.

but It is not matching..

debugging result.

when normal status

ex)

cFIFO[0] -> eQADC -> rFIFO[0]

cFIFO[1] -> eQADC -> rFIFO[1]

cFIFO[2] -> eQADC -> rFIFO[2]

cFIFO[3] -> eQADC -> rFIFO[3]

TNXTPTR = 0, RFCTRx = 0,  POPNXTPTRx = 0

TNXTPTR = 1, RFCTRx = 0,  POPNXTPTRx = 1

TNXTPTR = 2, RFCTRx = 0,  POPNXTPTRx = 2

TNXTPTR = 3, RFCTRx = 0,  POPNXTPTRx = 3

but, abnormal status(when i added some function)

cFIFO[0] -> eQADC -> rFIFO[2]

cFIFO[1] -> eQADC -> rFIFO[3]

cFIFO[2] -> eQADC -> rFIFO[0]

cFIFO[3] -> eQADC -> rFIFO[1]

TNXTPTR = 0, RFCTRx = 3,  POPNXTPTRx = 2

TNXTPTR = 1, RFCTRx = 3,  POPNXTPTRx = 4

TNXTPTR = 3, RFCTRx = 4,  POPNXTPTRx = 0

                   :

TNXTPTR = 2, RFCTRx = 1,  POPNXTPTRx = 3

What is causing this problem?

Please give an answer.

[davidtosenovjan]

I believe you will find an answer in attached file. Let me know if it helps or not.

[najongmin]

Thanks for your answer.

But My sytem already has 2 cQueue and 2 rQueue.

so, your solution is not ture of my system.

In more detail, (adc read trigger = software trigger used)

cQueue0[0:9] ---- eDMA ch0 ----> ADC0 ----- eDMA ch1 ----> rQueue0[0:9], this routine execute every 200us.

cQueue1[0:9] ---- eDMA ch2 ----> ADC1 ----- eDMA ch3 ----> rQueue1[0:9], this routine also execute every 200us.

Futermore, I guess this problem cause is stack overflow.

In the past, I did solve this problem by extending stack size.

but, I can not be sure whether a coincidence.

I guess cQueue influence of stack overflow.

e.g.

cQueue0[0] = fault command -----> rQueue[0] = cQueue0[2]'s result

cQueue0[1] = fault command -----> rQueue[0] = cQueue0[3]'s result

cQueue0[2] = right command -----> rQueue[0] = ?????

cQueue0[3] = right command -----> rQueue[0] = ?????    <==== queue underflow arisen.

But...

as you know, In the SRAM, stack area and data(global variable decleration area) area are seperated defnitely.

So I'm not sure this problem's reason.

Please give me furthermore solution.

[davidtosenovjan]

Does your eQADC setting have enabled ABORT feature (EQADC_MCR[IECAn] = 1) ?

[najongmin]

No

My EQADC_MCR setting value is 0x00000000

Is it right??

[davidtosenovjan]

Yes, it is. I have asked because there is an erratum e5086 it's consequence may look like as result swap as well. Currently published here:

http://cache.freescale.com/files/microcontrollers/doc/errata/MPC567xF_3M17W.pdf

However if you don't have activated ABORT feature, it'll not be the reason.

Another point is that XBAR priority for eDMA master must be set for higher value than the core (do you have it so?), it is strongly recommended for DMA driven application for those slaves where DMA sources/destinations are located (PBRIDGE and SRAM in your case). Pay attention to XBAR_MPRx registers.

[najongmin]

Thanks David.

Your seggestion is very effective.

When I change the XBAR Master's priority, (Higher eDMA priori