activation of Input Glitch Filter of EMIOS input channel of MPC5777c

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

activation of Input Glitch Filter of EMIOS input channel of MPC5777c

485 Views
dineshmoka
Contributor III

hi I am using MPC5777c EMIOS module for input period measurement and am using input glitch filter for EMIOS_0 channel 2. In RM they have mentioned some programming guidelines like

1.Program the SoC pin mux logic to route an external signal to the input of the selected glitch filter

2.Enable the clock source at the SoC level.

how to program the SoC pin mux logic to route an external signal and how to enable the clock source to the Soc?

0 Kudos
1 Reply

479 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi

this is probably description taken from IP
1) IGF connection with eMIOS/eTPU channels is given and stated in the chapter 39.1.3 IGF interaction with other modules of the RM 
2) IGF is running from eTPU_clk which is still enabled. There is MDIS bit in IGF channel IGF_MCRn register, but it is cleared by default, so clock is enabled.

You can refer to simple IGF example on https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-eMIOS-IGF-test-GHS614/ta-p/1101...

 

BR, Petr

0 Kudos