Whether each eMIOS channel(0-23) supports SAIC and OPWFMB mode in MPC5644A ?

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Whether each eMIOS channel(0-23) supports SAIC and OPWFMB mode in MPC5644A ?

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plabgh
Contributor I

I have two questions:

 

1、Whether all eMIOS channel(0-23) can generate variable period and duty cycle PWM through set MODE[0:6]=10110b0 in MPC5644A ?

 

2、In SAIC mode, whether I need use eMIOS[23] channel to drive the global counter (Counter bus A) ?

In other words, whether each eMIOS channel(0-23) can use internal counter to capture the counter values on the edges,

rather than use Counter bus A ?

 

In MPC5634M, i can only generate variable period and duty cycle PWM on Big channels (0, 8, 9, 10, 12, 14, 15, 23) through set MODE[0:6]=10110b0.

In MPC5634, I find that Big channels (0, 8, 9, 10, 12, 14, 15, 23) can use internal counter to capture the counter values on the edges, other channels can not.

I don't know why, it may be my configure err.

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

 

1) It depends. There is difference between MCU revisions with respect of eMIOS channels on MPC5644A.

Rev 1 and Rev 1.1:

•Small Channels : 1, 3, 5 & 6        (GPIO, SAIC, SAOC)

•Medium Channels : 2, 4, 11, 13                (Above + OPWMB)

•Big Channels : 0, 7-10,12,14-23 (Above + IPM, IPWM, DOAC, MCB, OPWFMB)

Rev 2

•Big Channels: 0 – 23

You can read SIU.MIDR register and determine which revision you have, lowest 8bit determine mask:

0x00 … rev1

0x01 … rev1.1

0x10 … rev2

2) If you will use big channel, for example channel 0, the SAIC mode will work also for internal counter selected. Sure you have to enable prescaler for that channel by UCPREN bit.

Internal counter is not implemented on small and medium channels.

Please refer to the chapter “eMIOS200 UC Counter Register (EMIOS_CCNTR[n])” of the RM. It is written there that the internal counter should not be implemented in some eMIOS channels. If it is not implemented then selecting internal counter as time base will not work.

BR, Petr

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