Hello,
eTPU and eMIOS. This are independent IOs right?
eMIOS is periphery (IP) and eTPU is processing core (its ASIC)
So I can independently choose which to go high and which to go low?
Not sure about this, but if you are talking about signal levels, then yes.
Why does only eTUPB and eMIOS have the full 32 pin i/o?
If you are asking about board implementation, then it is because the design decided that way.
can you clarify what TP51-52 and TP55-58 correspond to?
TP = test point. Not sure what document you are referring to.
Check out MPC5775BE EVB User Guide for details.
Best regards,
Peter