My question is on the UJA1023 chip spec sheet, Example 1 on page 22 of 49.
New to LIN, though I have studied other protocols and I think I understand most of the message structure.
This example is almost exactly what I'm looking for in my application. I want to set the chip for 8 outputs and be able to switch on any combination of those outputs that I want. I'm working to understand the first 10 lines and the configuration that is required for the chip. Haven't decided if I want them HSE or LSE yet, but that appears easy enough to configure. Looks like I want level set for all. Don't need PWM.
My question is after the first 10 lines. There is no NAD in the following 8 lines. How does the slave chip know it is the receiver of these messages?
Hello, UJA1023 input is what mean?How to set up in the program?thank you. SB SF 80 whats meaning ?why need UJA1023 input ? Input triggers an IO, UJA1023 how to inform the host, return the data?thank you can you give me a example?
The UJA1023 uses one LIN command “PxReq” to receive data and one “PxResp” to transmit data respectively. The IDs for PxReq and PxResp are configured by means of the ‘assign frame ID’ command. That is the first line in the example, ID(PxReq) = 04,ID(PxResp) = 05.
So finally the Px outputs are set with the “PxReq” frame where the PID (protected Identifier; parity + ID) is transmitted. So if the ID is 0x04, the PID is 0xC4 which is actually transmitted, as example shows.
For the PxResp frame, that is used to read inputs etc, the assigned ID is 0x5. So the PID is 0x85.
Hello, UJA1023 input is what mean?How to set up in the program?thank you.
SB SF 80 whats meaning ?why need UJA1023 input ?
Input triggers an IO, UJA1023 how to inform the host, return the data?thank you