The FEC can't clear the R bit in the TxBD on MPC5675K.

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The FEC can't clear the R bit in the TxBD on MPC5675K.

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yachuanliu
Contributor II

Hi everybody,

For some reasons, we used a core optimization example got from Freescale to increase the CPU operating rate. Then when I transplant the FEC program to the core optimization example, the FEC can’t clear the R bit in the transmit buffer descriptors. But The MPC5675K FEC can clear the TxBD’s R bit in the official FEC demo, and the R bit can be cleared when I delete the “DCache_init()” in the "Core_optimizations()"(you can find these program in the below accessory "Optimization.c").

Then, I would like to know how to solve this problem without deleting the “DCache_init()”. If the information is not enough, please contact me. Thank you.    

Best regards.

YaChuan !

Original Attachment has been moved to: Optimizations.c.zip

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martin_kovar
NXP Employee
NXP Employee

Hi,

it should be known issue which occurs when DMA and cache is used together. DMA read/write to RAM on background and cache is not updated. Now data integrity is broken and this causes your problem.

This is copied from reference manual:

The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in

one or more buffers. Associated with each buffer is a buffer descriptor (BD) that contains a starting address

(pointer), data length, and status/control information (which contains the current state for the buffer). To

permit maximum user flexibility, the BDs are also located in external memory and are read in by the FEC

DMA engine.

So first possibility is disable Dcache, but there is also another way. You can choose part of the RAM memory, which will not be cached. So find the memory area, which is used by FEC and disable caching for this area.

Look at the following document and read chapters MMU and Cache. You should find there all necessary information how to disable RAM line caching.

e200 Core Training relevant to MPC55xx and MPC56xx device family

Regards,

Martin

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487 Views
martin_kovar
NXP Employee
NXP Employee

Hi,

it should be known issue which occurs when DMA and cache is used together. DMA read/write to RAM on background and cache is not updated. Now data integrity is broken and this causes your problem.

This is copied from reference manual:

The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in

one or more buffers. Associated with each buffer is a buffer descriptor (BD) that contains a starting address

(pointer), data length, and status/control information (which contains the current state for the buffer). To

permit maximum user flexibility, the BDs are also located in external memory and are read in by the FEC

DMA engine.

So first possibility is disable Dcache, but there is also another way. You can choose part of the RAM memory, which will not be cached. So find the memory area, which is used by FEC and disable caching for this area.

Look at the following document and read chapters MMU and Cache. You should find there all necessary information how to disable RAM line caching.

e200 Core Training relevant to MPC55xx and MPC56xx device family

Regards,

Martin

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yachuanliu
Contributor II

Got it. Thank you very very very much.

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martin_kovar
NXP Employee
NXP Employee

You are welcome :smileyhappy:.

Martin

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