I used PWM-CTU-ADC-DMA patterns in developing motor controls based on MPC5741P, and DMA's end-of-major loop interrupt(INTMAJOR) is enabled. Now the question is that
CTU has the right trigger frequency, but ISR is triggered again just after it has run, and it's going to keep doing that.
TCDn CSR[DONE] flag bit cannot be cleared by writing 1 to DMA_CDNE[CADN].
DMA Channel 0 init:
void DMA_Channel_Config(u8 DAM_channel,u32 src,u32 dst)
{
DMA_0.ERQ.B.ERQ0 = 0; //The DMA request signal for channel 0
DMA_0.TCD[DAM_channel].SADDR.R = src;
DMA_0.TCD[DAM_channel].SOFF.R = 0;
DMA_0.TCD[DAM_channel].SLAST.R = 0;
DMA_0.TCD[DAM_channel].ATTR.B.SMOD = 0;
DMA_0.TCD[DAM_channel].ATTR.B.SSIZE = 1;
DMA_0.TCD[DAM_channel].DADDR.R = dst;
DMA_0.TCD[DAM_channel].DOFF.R = 2;
DMA_0.TCD[DAM_channel].DLASTSGA.R = -16;
DMA_0.TCD[DAM_channel].ATTR.B.DMOD = 0;
DMA_0.TCD[DAM_channel].ATTR.B.DSIZE = 1;
DMA_0.TCD[DAM_channel].CSR.B.DREQ = 0; /*The channel’s ERQ bit is not affected*/
DMA_0.TCD[DAM_channel].NBYTES.MLNO.B.NBYTES = 16;
DMA_0.TCD[DAM_channel].BITER.ELINKNO.B.ELINK = 0;
DMA_0.TCD[DAM_channel].BITER.ELINKNO.B.BITER = 1;
DMA_0.TCD[DAM_channel].CITER.ELINKNO.B.ELINK = 0;
DMA_0.TCD[DAM_channel].CITER.ELINKNO.B.CITER = 1;
DMA_0.TCD[DAM_channel].CSR.B.INTHALF = 0; /* No interrupt when major count half complete */
DMA_0.TCD[DAM_channel].CSR.B.INTMAJOR = 1; /*interrupt when major count completes */
DMA_0.TCD[DAM_channel].CSR.B.MAJORELINK = 0; /* Dynamic program is not used */
DMA_0.TCD[DAM_channel].CSR.B.MAJORLINKCH = 0; /* No link channel # used */
DMA_0.TCD[DAM_channel].CSR.B.ESG = 0; /* Scatter Gather not Enabled */
DMA_0.TCD[DAM_channel].CSR.B.BWC = 0; /* Default bandwidth control- no stalls */
DMA_0.TCD[DAM_channel].CSR.B.START = 0; /* Initialize status flags START, DONE, ACTIVE */
DMA_0.TCD[DAM_channel].CSR.B.DONE = 0;
DMA_0.TCD[DAM_channel].CSR.B.ACTIVE = 0;
DMA_0.ERQ.B.ERQ0 = 0x1; //The DMA request signal for channel 0
}
The location of the ISR in the intc_SW_mode_isr_vectors_MPC5744P.c:
(uint32_t) &dummy, /* Vector # 50 Reserved for Platform periodic timer 3_2 (STM) */
(uint32_t) &dummy, /* Vector # 51 Reserved for Platform periodic timer 3_3(STM) */
(uint32_t) &dummy, /* Vector # 52 eDMA Combined Error eDMA */
(uint32_t) &HW_eDMA_Channel0_ISR, /* Vector # 53 eDMA Channel 0 eDMA */
(uint32_t) &dummy, /* Vector # 54 eDMA Channel 1 eDMA */
(uint32_t) &dummy, /* Vector # 55 eDMA Channel 2 eDMA */
(uint32_t) &dummy, /* Vector # 56 eDMA Channel 3 eDMA */
