Synchronization issue in DMA of MPC56

[meedandeys]

Hello  Folks,

I am facing below issue with DMA and UART on MPC5646C, any help would be appreciated.

I am using 2 UART channels on MPC5646C for communication with other devices. I have configured UART1 RX/TX to use DMA channels 0,1 and UART2 RX/TX to use DMA channels 2,3.

Communication happens smoothly on UART1/2 initially, however after ~6 hrs, UART1 RX goes out of synchronization. i.e. on UART1 RX/DMA I see only partial data (~16 bytes out of 20 bytes).

Directions on this issue would be greatly appreciated.

[davidtosenovjan]

XBAR priority for eDMA master should be set for higher value than the core. Do you have it so? Don't you see UART FIFO overflow after this error?

[meedandeys]

Hello David,

Thank you for your help. XBAR is not being used in my current configuration. There are no UART FIFO overflows in this situation. In the DMA i have set up TCD with a configuration of Major = 20 bytes and Minor = 1 byte with no channel linking. I am running a command-response functionality on the UART channel. Command is of 2 bytes and response is of 20 bytes. In the DMA buffer i see 20 bytes of data, out of which 4 bytes of data is out of synchronization. i.e. I see my frame start at Index =4 (expected is at index 0), the data bytes coming at the beginning are of the previous command.

Note: Communication seems to be working correctly at the start, however after long executions ~7-12 hrs, the DMA channel is going out of sync.

Any advice on this issue would help.

[davidtosenovjan]

XBAR cannot be unused as it is a crossway of internal busses. But I understand you mean you don’t touch default XBAR configuration.

XBAR priority for eDMA master must be set for higher value than the core, it is strongly recommended for DMA driven application for those slaves where DMA sources/destinations are located (PBRIDGE and SRAM in your case). Pay attention to XBAR_MPRx registers.

[meedandeys]

Hello David,

Thank you for your help. Yes, I am using the XBAR registers default values. I have not worked much on the XBAR switch, and hence quiet apprehensive to update the default settings.

I went through the Master Priority Registers (MPRn) of MPC5646C RM, however I could not find out what should be the registers set to ?

Right now my configuraiton of MPR0 to MPR7 is set to AULB = 000 (No Arbitration).

I am just wondering if the XBAR switch could result in a loss of synchronization for DMA ? Can you please help me understand ?

Appreciate your help !!!

[meedandeys]

Correcting the typo in my post.

I went through the Master Priority Registers (MPRn) of MPC5646C RM, however I could not find out what should be the registers set to ?

Right now my configuration of MPR0-3,7 is set to MSTR_7 to MSTR_0 = 000 (This master has highest priority).

Should i Change the configuration as MPR2-3,7  to Field -MSTR_2  = 000 and MSTR_7 to MSTR_0(except MSTR_2) = 111 ?

Please advise

[meedandeys]

The problem was solved by enabling/disabling the DMA channels using write to DMA.SERQ register

Thanks,