Setting LINFlexD DMATXE/DMARXE for ports > 0 on MPC5777M?

cancel
Showing results for 
Search instead for 
Did you mean: 

Setting LINFlexD DMATXE/DMARXE for ports > 0 on MPC5777M?

Jump to solution
1,070 Views
chrismorrison
Contributor II

Hi,

 

I would like to enable DMA on the LINFlexD ports of the MPC5777M.

Part of this involves setting the DMATXE and DMARXE registers.

 

Setting the values on port 0 works:

LINFlexD_0.DMATXE.R = 0x00000001; /* register is updated */

LINFlexD_0.DMARXE.R = 0x00000001; /* register is updated */

 

Trying to do the same on any of the other ports seems to have no effect

LINFlexD_1.DMATXE.R = 0x00000001; /* register is not updated */

LINFlexD_1.DMARXE.R = 0x00000001; /* register is not updated */


Is there something else required before these registers are writable?  Any suggestions would be appreciated.


Thanks,

Chris



Labels (1)
Tags (3)
1 Solution
528 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi Chris,

Seems Peter is not completely correct.

The DMA is working from all LINFlexD modules, also for both RX/TX in the UART mode.

The highlighted sentence means that for UART and LIN Master mode just lowest bit in DMATXE/DMARXE can be programmed.

The issue, you are able to program those registers only for LINFlexD_0, is little bit hidden.

The LINFlexD_0 is the only module which has LIN Slave implemented and so Filter registers (IFCRx) are available. Those are missing on other LINFlexD_x modules as it is LIN Master only. If you look over next registers description in the RM (GCR, UARTPTO, UARTCTO, DMATXE, DMARXE) there is sentence “The address offset depends on the no_of_filters.”

Thus the addresses of above registrers are shifted in the LINFlexD_1/2/14/15/16 modules.

So try to write value “1” to IFCR3 to modify DMATXE and to IFCR4 to modify DMARXE.

The DMA should work then. Don't forget to properly set the DMAMUX too. Also FIFO mode have to be set in UARTCR.

Regards,

Petr

View solution in original post

0 Kudos
4 Replies
528 Views
petervlna
NXP Employee
NXP Employee

Hi Chris,


The DMATXE and DMARXE registers can be set only for LIN channel 0. Therefore you are not able to set them for other channels.

However the part “master mode only” is not clear to me as I can set it also in Slave mode.

pastedImage_0.png

Peter

0 Kudos
528 Views
chrismorrison
Contributor II

Hi Peter,

Thanks for your reply.  Ideally I would like to use two or three UARTs from one of the computational cores, with Tx/Rx handled in the background by DMA, but if I understand correctly then this is not possible?

Is there an alternative that you would suggest which would minimise the overhead on the computational core?  The options appear to be:

- Use interrupts on the computational core to service the UARTs

- Have another core (e.g. the I/O core) handle UART Tx/Rx, with some kind of shared memory & signalling mechanism between the two cores

- Poll the UARTs (not practical for high data rates)

>> "However the part “master mode only” is not clear to me as I can set it also in Slave mode."

I think this is saying that multiple LINFlexD ports can use DMA if they are configured in 'LIN Slave mode', but only port 0 can use DMA if using the ports in 'LIN Master' or UART mode.  This would also explain why the LINFlexD DMA demo MPC5643L UART examples only uses port 0.

Best regards,

Chris

0 Kudos
529 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi Chris,

Seems Peter is not completely correct.

The DMA is working from all LINFlexD modules, also for both RX/TX in the UART mode.

The highlighted sentence means that for UART and LIN Master mode just lowest bit in DMATXE/DMARXE can be programmed.

The issue, you are able to program those registers only for LINFlexD_0, is little bit hidden.

The LINFlexD_0 is the only module which has LIN Slave implemented and so Filter registers (IFCRx) are available. Those are missing on other LINFlexD_x modules as it is LIN Master only. If you look over next registers description in the RM (GCR, UARTPTO, UARTCTO, DMATXE, DMARXE) there is sentence “The address offset depends on the no_of_filters.”

Thus the addresses of above registrers are shifted in the LINFlexD_1/2/14/15/16 modules.

So try to write value “1” to IFCR3 to modify DMATXE and to IFCR4 to modify DMARXE.

The DMA should work then. Don't forget to properly set the DMAMUX too. Also FIFO mode have to be set in UARTCR.

Regards,

Petr

0 Kudos
528 Views
chrismorrison
Contributor II

Hi Petr,

Ah, I understand now, thank you.

Some text like yours in the next revision of the RM and/or providing two different LINFlexD_tags in the mpc5777m.h file

  - one mapped to port 0, which has an IFCR[16] member

  - another mapped to ports 1/2/14/15/16, that doesn't have the IFCR[16] member, so that GCR, UARTPO, etc. are memory-mapped correctly

would be helpful.

(but I do appreciate that the RM does already contain the correct information - this is just an observation that your explanation is clearer to someone who is unfamiliar with LINFlexD and would just like some UARTs).

Thanks again,

Chris

0 Kudos