void fft_spt_fft256(uint32_t input_start, uint32_t output_start, tdPar* par){
uint32_t wr_val;
uint32_t i;
// Define how to read words from RAM
if( par->chipset == chipsetKestrel ){
// 7 word SKIP in SRAM, 1 word continuous(Used to read a channel in 8-channel Tile 4)
wr_val = 0x01007001;
}
else{
// 2 word SKIP in SRAM, 1 word continuous(Used to read a channel in 3-channel Tile 4)
wr_val = 0x01002001;
}
/* Mem location of the first input & location where first output is placed
are populated by dummy values (0xDEADBEEF)
They are modified after array initialization */
uint32_t instructSet[] = {
// LOOP - 64 times 新增修改
0x14000040, 0x00000000, 0x00000000, 0x00000000,
// Load Samples
// Sign extend, direct, 16-bit real pack
// synchronous, VEC_LEN = 64(0x040) * 64-bit SRAM words = 512 bytes
// The 512 bytes contain all 256 * 2 byte SDADC samples for 1 chirp
// PDMA SRAM(SAMPLE_SRAM_START) -> OPRAM (0x8000)
// x word SKIP in SRAM, y word continuous(Used to read a channel in n-channel Tile 4)
0xA18D0040, input_start, 0x80000000, wr_val,
// ADD command: increment SRAM offset in FFT result buffer to next chirp
// ADD, immediate data, no left shift, 24bit modulo?
// SRC1 is work register 0, DEST is work register 0
// SRC2 is work register 0(n/a)
// immediate data = 0x000010000000: WR[0].IM += 0x1000, WR[0].RE += 0x0000
0x0C00001F, 0x00000000, 0x00000000, 0x00001000,
// FFT 265 RDX4 instruction w/ real input
// input @0x8000, twiddles @0x4000, window @0x4500 output @0xA000
// pad with 4 LSBs
//0x84000100, 0x80008100, 0x00000101, 0x7fff0040,
// Win and pre-scaling << 8
0x84000100, 0x80008100, 0x45000101, 0x00010250,
// fixed scaling
// RDX4, round 0 and pre-scaling << 1
0x88030100, 0x81009000, 0x40000101, 0x00000010,
// RDX4, round 1
0x8a110100, 0x9000A000, 0x40000101, 0x00000000,
// RDX4, round 2
0x8a210100, 0xA0009000, 0x40000101, 0x00000000,
// RDX4, round 3
0x8a310100, 0x9000A000, 0x40000101, 0x00000000,
// PDMA transfer of output to SRAM
// Sign extension, direct address, 24-bit complex
// PDMA OPRAM (0x9000) -> SRAM (OUTPUT_SRAM_START), synchronous,
// Vec len = 256 units, no skip (continuous transfer)
0xA1870100, output_start, 0x00080000, 0x01000004,
// ADD command: increment work register for next loop
// ADD, immediate data, no left shift, 24bit modulo?
// SRC1 is work register 1, DEST is work register 1
// SRC2 is work register 0(n/a)
// immediate data = 0x000008000080: WR[1].IM += 0x0008(move to next bin), WR[1].RE += 0x0400
0x0C00001F, 0x00080008, 0x00000000, 0x00000400,
// NEXT loop
0x18000000, 0x00000000, 0x00000000, 0x00000000,
// Stop Cmd
0x10000000, 0x00000000, 0x00000000, 0x00000000
};
//Write the set of commands into memory for SPT to fetch
for(i=0;i<sizeof(instructSet)/sizeof(uint32_t); i++)
{
wr_val = instructSet[i];
*(vuint32_t*)((FFT_INSTRUCTION_START) + (i*4))= wr_val;
}
SPT.CS_STATUS0.R = 0xFFFFFFFF; // RESET all status register
//SPT.GBL_CTRL.R = 0x0; // RESET Ctrl
//SPT.GBL_CTRL.B.SPT_EN = 0; // RESET SPT
SPT.CS_PG_ST_ADDR.R =FFT_INSTRUCTION_START; // instructions start address
//SPT.GBL_CTRL.R = 0x1F; // Enable SPT, ACQ & start command sequencer
SPT.GBL_CTRL.R = 0x1D; // Enable SPT & Program start control
//SPT.GBL_CTRL.B.SPT_EN = 1; // Enable SPT & Program start control
while ((SPT.CS_STATUS0.R&0x8)!=0x8){} // Wait until SPT finished commands
}
The program will stop at the last statement
“ while ((SPT.CS_STATUS0.R&0x8)!=0x8){} // Wait until SPT finished commands”
Hi,
if it is command errors,you can read the relevant bit of SPT_CS_STATUS1 , SPT_DMA_ERR_STATUS
, SPT_HW_ACC_ERR_STATUS ,if it is non-command errors,you can read the relevant bit of SPT_MEM_ERR_STATUS
, SPT_DMA_ERR_STATUS, SPT_HW_ACC_ERR_STATUS , All bits of SPT_HIST_OVF_STATUS0 , All bits of SPT_HIST_OVF_STATUS1 .Last,before the start,best to let the command sequencer at RST state.
Thanks for your help, I found the wrong flag in the register。But I still did not solve the problem,As I mentioned earlier, I just want to change the input and output address in a loop, I do not know where the problem