SPI Timeout Delay Calculation on MPC5674F

[CNarendra]

Hello,

I am working on an SPI driver for the MPC5674F microcontroller, which runs at 264 MHz, and I need to calculate the timeout delay for a polling-based SPI transaction. The SPI transfer completion is monitored using the Transfer Complete Flag (TCF), with a timeout based on iteration count. 

System Clock Details:

• MCU Frequency = 264 MHz
• Clock Period = 1/264MHz = 3.78787879 ns (approx. 3.79 ns per cycle)

Code Snippet:

#define SPI_MAX_WAIT_ITERATIONS 100

// Wait until the transfer is complete.
// The TCF bit indicates that all bits in a frame have been shifted out.
while (p_spi_config->port->SR.B.TCF == 0)
{
    if (iteration_counter++ > SPI_MAX_WAIT_ITERATIONS)
    {
        // If this point is reached, the SPI transfer did not complete
        // within the expected iterations.
        spi_status = eSPI_TIMEOUT;
        iteration_exceeded = true; // Set flag to break `for` loop
        break;                     // exit from while loop
    }
}

Delay Calculation:

Assuming iteration consists of:

1. Reading the TCF bit (p_spi_config->port->SR.B.TCF == 0) → 2 cycles
2. Incrementing iteration_counter → 1 cycle
3. Comparing iteration_counter > SPI_MAX_WAIT_ITERATIONS → 1 cycle
4. Branching back to loop start → 1 cycle

Total per iteration ≈ 5 clock cycles

IF SPI_MAX_WAIT_ITERATIONS = 100, total cycles before timeout:

Total Cycles =   100×5  =  500
Total Time    =  500×3.79 ns  =  1.89 microseconds

Questions:

1. Is this delay calculation correct for the MPC5674F?
2. Is 100 iterations a reasonable timeout, or should it be adjusted?
3.  MPC5674F SPI module doesn't have any flags to detect errors like overrun ,frame errors etc as per status register . is there any way to detect errors ?

Any insights from the community would be greatly appreciated!

Thanks in advance!

Narendra C

MPC5674F , #POWERPC ARCHITECTURE

[PetrS · Accepted solution]

Hi,

1) it will be more and not such straightforward you outlined. You should rather see how code is compiled and based on assembler code you can guess more, with help of instruction set  states in Core manual. However another setting on MCU, like I/D caches, memory wait states, crossbar setting/latency, comes into role.
But you can use some internal timer or simply toggle some pin to measure specific code execution time.
2) Depends on actual SPI transfer/bitrate setting
3) there is TXFIFO underflow and RXFIFO overflow indication. As transfer attributes are set prior to communication, must be same on Master/Slave, and SPI is synchronous communication with serial clock no such errors are expected.

BR, Petr