SDADC in wraparound mode with DMA

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SDADC in wraparound mode with DMA

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abul_fazal
Contributor II

Below code snippets is for sdadc in wraparound mode (taking data from channel 0->1->2->3)

and then storing in an array with four elements. I'm facing synchronization issue, since here we don't have much control over FIFO which triggers DMA when it is full. How will we transfer the data from CDR register to different elements of array(0th element for channel 0,1st element for channel 1,2nd element for channel 2,3rd element for channel 3)??

Doubt:

since the source is CDR reg with 0 offset then how the data after FIFO gets full will get transferred to the respective elements of an array?? 

static uint32 s32Sdadc_0_Channels_inmv[4] = {0,};

static uint32 s32Sdadc_0_Channels[4] ={0,};

#define SDADC_0_RQUEUE0_ADDRESS (uint32)(&s32Sdadc_0_Channels)
Mcl_DmaTcdAttributesType SdadcDMAChannel36Config = {/** SDADC1 CDR to SDADC RQUEUE0 DMA_A Channel 36 */
(uint32)(&SDADC_1.CDR.R), /** Source Address */
(uint32)SDADC_0_RQUEUE0_ADDRESS, /** Destination Address */
(uint32)2U, /** Source Size */
(uint32)2U, /** Destination Size */
(uint32)0U, /** Source Address Offset */
(uint32)4U, /** Destination Address Offset */
(uint32)0U, /** SMOD */
(uint32)0U, /** DMOD */
(uint32)4U, /** number of bytes to be transferred */
(uint32)4U, /** number of iterations */
};

Mcl_DmaTcdType * pTcdAddress;
pTcdAddress = (Mcl_DmaTcdType *)Mcl_DmaGetChannelTcdAddress((Mcl_ChannelType)MCL_DMA_LOGICAL_CHANNEL_12);
Mcl_DmaConfigTcd(pTcdAddress, &SdadcDMAChannel36Config);
Mcl_DmaTcdSetFlags(pTcdAddress, (uint8)(0x0 | DMA_TCD_INT_MAJOR_U32));
Mcl_DmaTcdSetDlast(pTcdAddress, -(sint32)16);
Mcl_DmaEnableHwRequest(MCL_DMA_LOGICAL_CHANNEL_12);

following function is being called in 10 msec task-

SDADC_1.STKR.R = 0xFFFF; 
uint32 tempitr=0;
for(tempitr=0; tempitr<SDADC0_CHANNELS_CONFIGURED; tempitr++)
{ 
s32Sdadc_0_Channels_inmv[tempitr] = ((5000*s32Sdadc_0_Channels[tempitr])/(0x7FFFU));
SDADC_1.SFR.B.DFORF =1U;
}
Mcl_DmaEnableHwRequest(MCL_DMA_LOGICAL_CHANNEL_12);

Thank you in advance.

Hoping to get reply soon

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I am apologizing, I was trying for a while to understand your issue, without success. Could you clarify what actually you want to achieve? Could you simplify it a bit? Thanks

View solution in original post

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namnguyenviet
NXP Employee
NXP Employee

Hi davidtosenovjan‌,

I'm following with Fazal in a similar topic: 

Can SDAC work in wraparound mode with DMA in MPC5777C?? 

I think his problem is not kinda related to timing of trigger SDADC conversion, but related to during conversion time until SDADC buffer is full and DMA request is triggered, and Fazal is (perhaps) concerning if that conversion can be switched for each SD channel (i.e., a measurement is taken from channel AN1->2->3->4, stored in FIFO and trigger DMA to transfer the data). 

My understanding is the switching channel is not automatically, but need a trigger, maybe SW or HW, according to MPC5777C RM. So during a conversion before DMA is triggered, trigger needs to be called, but so far I couldn't do it with SW. I'm trying with HW, maybe eTPU.

Do you have any idea, or the behavior is normal? 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Yes, I have meant it so. Trigger needs to be done to switch channel.

If you change channel manual, sequence must be as follows:

MUX CHANGE

SDADC_x.CSR.B.ANCHSLEL = Changed

This MUST be followed by a RESET

SDADC_x.RKR.R = 0x5Af0

I am not sure how it works with wraparound mode, I suppose a trigger is enough.

I would also note that triggers are as follows:

pastedImage_2.png

Unfortunately I cannot test it as currently I as working on the force home office.

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namnguyenviet
NXP Employee
NXP Employee

Hi davidtosenovjan‌,

I was able to trigger SDADC, both SW and HW. For HW, I realized each time triggered by HW, the ADC conversion is kinda "refresh", even in wraparound mode. As we expected that the FIFO buffer counter will increase counting if a trigger happened, however the FIFO buffer counter will reset to zero. If I setup a infinite eTPU triggered, the conversion will never finished, since it's always refreshed. If I setup a eTPU triggered for 4 times in order to change the measure channel from 0->1->2->3, only the channel 3 was get result.

So I supposed the DMA couldn't work as abul.fazal@gmobis.com‌ expected. How do you think?

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abul_fazal
Contributor II

Thank you for the reply.

Let me elaborate my issue,

Following are the SDADC config -

Wrap around mode enabled,

FIFO Threshold 4,

ANCHSEL_WRAP 3,

single ended mode enabled,

DMA is triggered when FIFO gets full.

SW triggered conversion for SDADC

For DMA, the source address is the CDR register and the destination address is an array of size 4.

The idea is to integrate DMA with SDADC, and DMA should store the channel 0 data in first element of an array , channel 1 data in second element of array, channel 2 data in third element and channel 3 data in fourth element of array.As the TCD for the DMA has been configured in that way. The TCD config I shared earlier.

Issue -

** *** DMA replicates the same channel 0 data to all the elements of the array.

As in SDADC the source is the CDR register and the souce offset is 0 according to DMA config,so how can we move the datawords such that

the 1st dataword which belongs to channel 0 gets stored in 1st element of array,2nd dataword which belongs to channel 1 gets stored in 2nd element of array,3rd dataword which belongs to channel 2 gets stored in 3rd element of array,4th dataword which belongs to channel 3 gets stored in 4th element of array

In SDADC DMA takes data from CDR register and copies it to the destination array of 4 elements.As in mpc5777c the SDADC's FIFO architecture is not clearly mentioned.

So, for DMA the source address is that of CDR register with offset 0 so same data gets replicated in the other destination array elements although the channels changes with SW triggering.

The same is not the case with EQADC as the EQADC has its own FIFO architecture and while configuring TCD for DMA offset can be configured as per requirements.

Hoping to get reply soon,

Thank you.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

How often you are triggering SDADC conversion? After mux change there is tSETTLING time whne result data are invalid.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I am apologizing, I was trying for a while to understand your issue, without success. Could you clarify what actually you want to achieve? Could you simplify it a bit? Thanks

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