SDADC - Why it overrun the FIFO? - MPC5746R

[demian91]

When i set a frecuency of 100KHz, it overrun the FIFO so the flag SFR.B.DFORF=1. I cant understand why it happens.

MC_CGM.AC0_DC1.R = 0x80000000 | 0xC0000; //200Mhz/13, SD_CLK = 15,38MHz

MCR.B.EN=1;

MCR.B.MODE=1;

MCR.B.VCOMSEL = 3; //Singled

MCR.B.PGAN=0 //1 Gain

MCR.B.PDR=10; //OSR = 75

MCR.B.HPFEN = 0;

OSDR.B.OSD = 0xFF; //Maximum for safe

FCR.B.FE = 1;

FCR.B.FTHLD = 16;

RSER.B.DFFDIRE = 1; //Enable Interrupt

The frecuency of data fd is fd=fs/(2*OSR)=102,5KHz.

I start the conversion with:

RKR.B.RESET_KEY = 0x5AF0;

Then it interrupts the first time but with the flag SFR.B.DFORF=1. i not sure if my configuration is appropriate. Is there a application note about the proper configuration? for the other hand, i try to reset the block clearing the flag DFORF and DFFF disabling the block before and the reenabling setting the RESET_KEY but it not works.

Is i set a frecuency of 64KHz for example, it works fine.

[demian91]

Ok I read in the interrupt enabled with RSER.B.DFFDIRE = 1.

void SDADC1_Interrupt()
{

ValorAct = SDADC_1.CDR.R;
SDADC_1.SFR.R = 1;

PIN_CONMUTE()

}

Finally it worked with 200KHz because i disabled the RTI that interrupted every 5 miliseconds. I dont understand exactly how it overflow the FIFO or what is the purpose of this. But i change to DMA and is more efficient of course, thanks for the answer.

[petervlna]

Hello,

When i set a frecuency of 100KHz, it overrun the FIFO so the flag SFR.B.DFORF=1. I cant understand why it happens.

So most probably your SW/HW is not reading the converted results and FIFO will overflow.

Is i set a frecuency of 64KHz for example, it works fine.

Most probably you are reading results by SW, and it is not fast enough.

How do you read the data when you have valid conversion?

Best regards,

Peter