Hi, i trying to control a SDADC module state that has a DMA Channel that send the result of each conversion SDADC_CDR to the input of DECFILTER the register DECFILTER_IB. I need that the SDADC module works only in a time, activating the SDADC_RSER.GDIGE=1 bit, so i enable the input DMA_IRQ_EN for control through an eTPU channel.
When it turns on the input, it works but always in the start it triggers the overrun flag SDADC_RSER.DFORF, so the DMA not send a new value until clear the flag in an interrupt. it seems that when the input is turn off, the SDADC continue fill the FIFO so i need to stop also the module to prevent trigger the DFORF flag.
Is possible to make that?
Solved! Go to Solution.
It sounds as description in the following erratum:
To apply no.2 you will possibly to change XBAR configuration to have higher priority for DMA access than CPU access (for particular XBAR slave).
It sounds as description in the following erratum:
To apply no.2 you will possibly to change XBAR configuration to have higher priority for DMA access than CPU access (for particular XBAR slave).
Where is that? The errata 1N83M is the only it appears in the documents.