S32R274 Can't get DMEM(TCM) to operate anything near CPU clock Speed ?

[markthompson170]

I'm having trouble getting the DMEM to work at speed.

The spec says "Access latency (zero wait-states) is similar to that of a data cache"

My tests show that I am able to access the local DMEM at only 25% faster than main memory with the D-Cache Disabled.

When D-Cache is enabled it jumps 200% faster relative to Disabled cache, this indicates that the DMEM is being cached ?

This does not make sense unless the access are going the main AHB bus.

I have checked DCR 496 (DMEMCTL0)and it shows defaults.0x41B.

I changed it to not bypass decorated access 0x01B, no speed change.

I changed it to not bypass decorated access and disable ECC checking 0x00, no speed change.

Any idea what is happening here ?

[markthompson170]

Follow up – Solution found – Thanks to NXP support.

It seems that the DMEM/TCM uses the same Address space for both CPU port and Slave Port access under default conditions.

 And to use the DMEMCTL0[DMEM BASEADDR] mapping you must set the DMEMCTL0[DBAPD] bit to enable the remapping.

This allowed me to map the DMEM to fixed CPU port address while keeping the Slave ports address space separate.With linker script changes I was able to map memory segments in to the DMEM and allocate structures within DMEM segment.