Reg CS High and low in external flash example

[vignesh_v]

Hi,

   Im reffering the MPC5676R example for developing similar SPI interface with flash with that of MPC5777c .I have a clarification regarding some commands requiring chip select low and execute and make it high after it.

Where in this example is t executed ? is it in the PUSH and Push ENQ where the CONT bit is set and EOQ bit is set.

 the code snippet where its required is given below,

and if that is the case ALLOW Transfer is used for what. could u pl explain.

The below example is reffered.

https://community.nxp.com/docs/DOC-335461 

#define ALLOW_TRANSFER DSPI_B.SR.R = DSPI_SR_EOQF

#define WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY while (!(DSPI_B.SR.B.RFDF)) {}

#define WAIT_UNTIL_TxFIFO_IS_FULL DSPI_B.SR.R = DSPI_SR_TFFF; \
while (!(DSPI_B.SR.B.TFFF)) {}


#define continuous_command_for_PUSH(x) DSPI_PUSHR_PCS1 | \
DSPI_PUSHR_CTAS(1) | \
DSPI_PUSHR_CONT | \
DSPI_PUSHR_TXDATA(x)


#define end_command_for_PUSH(x) DSPI_PUSHR_PCS1 | \
DSPI_PUSHR_CTAS(1) | \
(uint32_t) DSPI_PUSHR_EOQ | \
DSPI_PUSHR_TXDATA(x)

#define PUSH(n) DSPI_B.PUSHR.R = continuous_command_for_PUSH(n)

#define PUSH_ENQ(n) DSPI_B.PUSHR.R = end_command_for_PUSH(n)

#define POP(n) n = (uint8_t) (DSPI_B.POPR.R); \
DSPI_B.SR.R = DSPI_SR_RFDF

void spi_flash_bulk_erase (void)
{
uint8_t status, dummy_var;

ALLOW_TRANSFER; // if previous command has set EOQ
PUSH_ENQ(WREN); // write enable command
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var); // discard one RxFIFO item


ALLOW_TRANSFER; // if previous command has set EOQ
PUSH_ENQ(BE); // bulk erase command
WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
POP(dummy_var); // discard one RxFIFO item


printf("Beginning of Bulk Erase... (several tens of second)\n\r"); fflush(stdout);

do
{
status = spi_flash_read_status_register();
}
while (status & WIP); // wait here until bulk erase is done

printf("Bulk Erase Done !\n\r"); fflush(stdout);

}

Kindly explain in context if possible.

Regards,

Vignesh

[davidtosenovjan]

Hi, I would like to note it is only example code, not an official driver.

macro PUSH sends data, letting CS line asserted

macro PUSH_ENQ sends data, negating CS line, also it set End of Queue flag (it pauses command execution)

macro 'ALLOW Transfer' clears End of Queue flag allowing command execution previously paused by PUSH_ENQ.

This way you may compose every SPI memory command per bytes with using of several PUSH and one PUSH_ENQ macros.

Example SPI memory command below:

    ALLOW_TRANSFER; // if previous command has set EOQ
 
    PUSH(READ_ID);  // read data bytes command
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
    POP(dummy_var); // discard one RxFIFO item
                                           
    PUSH(0x00); // most-significant byte of address
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
    POP(dummy_var); // discard one RxFIFO item
                                              
    PUSH(0x00); // middle byte of address
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
    POP(dummy_var); // discard one RxFIFO item
                                     
    PUSH(0x00); // least-significant byte of address
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
    POP(dummy_var); // discard one RxFIFO item
    
    PUSH(dummy_byte); // dummy byte for generating CLK to slave
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;
    POP(manufacturer_ID); // read useful data
    
    PUSH_ENQ(dummy_byte); // dummy byte for generating CLK to slave
    WAIT_UNTIL_RxFIFO_IS_NOT_EMPTY;                                               
    POP(device_ID); // read useful data

[vignesh_v]

Hi,

    Ok Thanks.

Regards,

Vignesh