Re-initializing CLK settings

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Re-initializing CLK settings

423 Views
Contributor III

Hi,

We are working with MPC5744P. In the application we have configured the PLL0 to be 160 MHz and PLL1 to be 200 MHz and out SYSCLK is based on PLL1(200 MHz). When we work with just the application, we correct see the tasks executing periodically, meaning 10ms tasks are executed every 10ms.

But, when we work with bootloader and the application, the see that the tasks executing at a different rate, meaning 10ms tasks are executed every 6.5ms. I believe clock settings are different in bootloader.

Questions:

Is there any way that we can re-initialize properly the clock setting in application? We are though initializing the correct settings that we want but I think it is not taking any effect. So, I was wondering if we can do at anytime? If we can, how would that be done?

Please note that, we don't access to bootloader as it is delivered by our supplier. I could ask them but I would like to have an option to change them in the application as well.

Thanks in advance.

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11 Replies

2 Views
NXP Employee
NXP Employee

Hi,

I've done debugging on your assembly code and I can see issue with mode transition at first:

see following pictures:

1. you have your PLL's off

pastedImage_2.png

2. You are connecting PLL0 PHI1 to AUX4 input for PLL1 generation:

pastedImage_3.png

3. But you have no PLL0 signal in this time.

4. The DRUN is your target mode and you are enabling both PLL's. PLL0 as source of PLL1 while you have no PLL0.

pastedImage_1.png

Your mode transition will fail and your system clock will stay IRC 16MHz. (I guess this is what you measure on output pin).

Solution:

----------

1. Configure PLL0 , do mode transition. (PLL1 disabled in ME_MC_DRUN)

2. Enable PLL1 in DRUN mode and do mode transition again

This is also described in Reference manual.

You can also use our PLL calculator :Excel MPC5744P Clock Configurator 

which generates code depending on Clock configuration.

Peter

2 Views
Contributor III

Thanks Peter. I hope you have checked  BootApplication.S19.

The application itself works correctly but it does not work in BootApplication.S19. I will cross verify these again and see what is happening.

Thanks for your time.

- Sagar

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2 Views
NXP Employee
NXP Employee

Yes,

I have checked bootapplicaiton.s19

and this is what I can see.

Peter

2 Views
NXP Employee
NXP Employee

Hello,

"Is there any way that we can re-initialize properly the clock setting in application?"

I expect every application first configure device (clocks, wait-states, peripherals, etc..) and then it starts executing application tasks.

Always verify is the change has taken effect before processing to the tasks.

You don't have touch bootloader. After bootloader execution finishes, you have to just simple do micro initialization in application.

Configure clocks according to your needs.

Peter

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2 Views
Contributor III

Hi Peter,

Thanks for responding. Yes, after bootloader finishes its execution, we are re-initializing in application; configuring the clocks as needed but it is not taking effect.

I got clarification from our supplier that they also use the same PLL and SYSCLK settings as we do. I don't understand why would they differ in behavior!

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NXP Employee
NXP Employee

Hi,

What do you see in MTRANS after your application mode change?

pastedImage_1.png

Did your micro takes mode change successfully?

Can you see on CLKOUT correct system clock.

Peter

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Contributor III

Hi,

It is 00 in both cases. Following is the register structure.

MC_ME_GS.JPG

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Contributor III

Here is what I measured CLK_OUT from both scenarios.

1. CLK_OUT when just application is run. You can see that frequency is 10MHz. With MFD = 20, SYSCLK=200MHz.

CLK_APP.png

2. CLK_OUT when bootloader and application is run. See that the frequency is 15MHz. I don't know what is MFD here and hence do not know that is SYSCLK. As per our supplier's statement, they say they have the same configuration as we do. So, something is not right. MFD cannot be 20 because 20*15MHz=300MHz, SYSCLK is not possible for this micro.

CLK_BL+APP.png

Please let me know if I have misunderstood anything wrong.

Thanks 

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2 Views
Contributor III

Here is an update:

When bootloader is ran, CLK_OUT is as follows:

(MFD=10. So, 20MHz * 10 = 200MHz)

Clock_Out_E0_Release.jpg

When Application is ran, CLK_OUT is as follows:

(MFD=20. So 10MHz * 20 = 200MHz)

CLK_APP.png

When both bootloader and application is ran, CLK_OUT is as follows:

CLK_BL_E0+APP.png

It looks like MFD is getting averaged. I don't know what exactly is happening.

Can someone help me please?

Thanks

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NXP Employee
NXP Employee

Ok,

When you measure 15Mhz (bootloader and application run) check the configuration of CGM (clock generation module) and check also settings of PLL.

Or send me your output file and i will check it. (the failing scenario)

Frequency always corresponds to clock configuration. (if you measure it directly on CLKOUT pin)

Peter

2 Views
Contributor III

Thanks for replying.
Sure, I am attaching all output files. Also, following are the details.

Bootloader:

Output file name: Bootloader.S19

PLLDIG_PLL0DV=0x4003203C;
PLLDIG_PLL1DV=0x00030014;

CLK_OUT = 20 MHz

Application:

Output file name: Application.S19

PLLDIG.PLL0DV.R = 0x40021014;

PLLDIG.PLL1DV.R = 0x00020014;

CLK_OUT = 10 MHz

Bootloader + Application:

Output file name: BootApplication.S19

CLK_OUT = 15 MHz.

** This is the failing scenario **

Thanks for the help.

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