Questions of MPC5777C FEC setting

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Questions of MPC5777C FEC setting

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taekyoungkim
Contributor II

Hi.

 

I try to enable FEC with MII interface setting, but nothing works so far.

I used 'AN4577_Using the Fast Ethernet Controller on the Qorivva MPC564xBC' document as a reference.

 

There are three questions about

1. FEC I/O setting

2. FEC Clock setting

3. isConnected() function (miiRead function)

 

Questions are below

1. FEC I/O setting - please check I/O setting

 

#define OBE    0x0200

#define IBE    0x0100

#define ODE    0x0020

#define SRC    0x0004

#define WPE    0x0002

#define WPS    0x0001

 

#define PA_GPIO 0x0000

#define PA_PRIM 0x0400

#define PA_ALT1 0x0800

#define PA_ALT2 0x0C00

#define PA_ALT3 0x1000

 

// initFecIo - initialise pads for FEC use in the SIU

void initFecIo(void)

{

        // MPC5777C - FEC MII-Lite mode IO setting

        SIU.PCR[99].R          = PA_ALT2 | OBE | IBE | SRC | WPE;              // FEC_MDIO

        SIU.PCR[109].R         = PA_ALT3 | OBE | WPE;                                 // FEC_MDC

 

        SIU.PCR[252].R         = PA_PRIM | ODE        | SRC;                         // FEC_TX_EN

        SIU.PCR[248].R         = PA_PRIM | ODE        | SRC;                         // FEC_TXD0

        SIU.PCR[251].R         = PA_PRIM | ODE        | SRC;                         // FEC_TXD1

        SIU.PCR[98].R          = PA_ALT2 | ODE        | SRC;                          // FEC_TXD2

        SIU.PCR[101].R         = PA_ALT3 | ODE        | SRC;                        // FEC_TXD3

        SIU.PCR[474].R         = PA_PRIM | IBE        | WPE;                        // FEC_TX_CLK

                                            

        SIU.PCR[100].R         = PA_ALT3 | IBE        | SRC | WPE;                  // FEC_RX_CLK

        SIU.PCR[249].R         = PA_PRIM | IBE        | WPE;                        // FEC_RX_DV

        SIU.PCR[250].R         = PA_PRIM | IBE        | SRC | WPE;                  // FEC_RXD0

        SIU.PCR[253].R         = PA_PRIM | IBE        | SRC | WPE;                  // FEC_RXD1

        SIU.PCR[110].R         = PA_ALT3 | IBE        | SRC | WPE;                  // FEC_RXD2

        SIU.PCR[107].R         = PA_ALT3 | IBE        | SRC | WPE;                  // FEC_RXD3

}

 

2. FEC Clock setting

  - According to 'MPC5777C_EVB_USER_GUIDE' document, on Board FEC 50MHz CLK is enable with J524 jumper setting. 

   175841_175841.pngpastedImage_3.png

  - With that jumper setting, if I set the 'MII Speed Control Register(FEC_MSCR)' with '0xA', it results in an 'FEC_MDC frequency 2.5MHz. Is that right?

175842_175842.pngpastedImage_4.png

 

3. isConnected() function 

  - It's kind of stuck in 'while (!isConnected())'

  - In my case, the miiRead return data is always '0x7849', so the 'result = (data & 0x0004) ? 1 : 0' is always '0'.

  - What is the meaning of register address value of '0x0001' in isConnected() function?

  - How can I pass and return expected data from miiRead() function? Please guide me.

 

// isConnected - returns 1 is connected, otherwise 0
int isConnected(void)
{
   uint16_t data;
   int result = 0;

   if (miiRead(0x0001, &data))
   {
      result = (data & 0x0004) ? 1 : 0;
   }
   return result;
}

 

int miiRead(int regAddr, uint16_t *data)

{

   ...

   FEC.MMFR.R = 0x60020000 | ((phyAddr & 0x1F) << 23) | ((regAddr & 0x1F) << 18);

}

 

I couldn't upload full source code for the security reasons, please refer 'AN4577SW' sample code.

If there are any advice, feedback or sample code, please let me know. 

 

Thank you for your patience.

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882 Views
thiagoduarte
Contributor II

Hi. 

I used the same configuration described in the last post. But it is not working.

Using wireshark the ARP packets generated by the processor is not received on the HOST.

The processor is receiving some packets sent by the HOST but with wrongly size and type.

I am using a MPC57xx MB Rev C,

The Jumper Configuration

J24 is 1-2.

J510 is 1-2.

J514 is 2-3.

The function isConnected is return TRUE when the cable is Connected.

Is it possible with a wrong clock configuration ?

I used the same clock configuration as the example Example_MPC5777C-PinToggleStationery.

Thanks 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

  1. Open drain for TX lines is not needed. If used there must be external pull-up. For some input pins you should also set SIU.IMUX0 register so pin will be connected with the module.
  2. The MDC frequency is calculated from the internal bus clock, in this case it should be PER_CLK selected by SIU_SYSDIV.PERDIV
  3. “0x0001” is address of the PHY status register BMSR, see PHY datasheet. The bit 2 - Link Status is checked, it is set once valid link is established.

Note: on Rev.A of the EVB minimodules the RXD2 and RXD3 are not directly connected to the PHY. Also there is no 50MHZ oscillator, which is needed for RMII mode. This is fixed on mini-modules of rev.B or higher.

BR, Petr

882 Views
taekyoungkim
Contributor II

Thank you for the reply.

I forgot to mention that the EVB is rev.C. 

I have corrected the I/O setting and the clock setting. 

1. There were some mistakes of I/O setting. It supposed to be OBE, not ODE. 
  - Also I added SIU_IMUX0 register setting for input pins, please check if I set it correctly.

// initFecIo - initialise pads for FEC use in the SIU
void initFecIo(void)
{
  // MPC5777C - FEC MII-Lite mode IO setting
  SIU.PCR[PCR99_FEC_MDIO_ALT2].R            = PA_ALT2 | OBE | IBE | SRC | WPE;     //FEC_MDIO
  SIU.PCR[PCR109_FEC_MDC_ALT3].R           = PA_ALT3 | OBE | WPE;                         //FEC_MDC

  SIU.PCR[PCR252_FEC_TX_EN_PRIM].R       = PA_PRIM | OBE | SRC;                         //FEC_TX_EN
  SIU.PCR[PCR248_FEC_TXD0_PRIM].R          = PA_PRIM | OBE | SRC;                         //FEC_TXD0
  SIU.PCR[PCR251_FEC_TXD1_PRIM].R          = PA_PRIM | OBE | SRC;                        //FEC_TXD1
  SIU.PCR[PCR98_FEC_TXD2_ALT2].R             = PA_ALT2 | OBE | SRC;                         //FEC_TXD2
  SIU.PCR[PCR101_FEC_TXD3_ALT3].R           = PA_ALT3 | OBE | SRC;                         //FEC_TXD3
  SIU.PCR[PCR474_FEC_TX_CLK_PRIM].R      = PA_PRIM | IBE | WPE;                         //FEC_TX_CLK

  SIU.PCR[PCR100_FEC_RX_CLK_ALT3].R      = PA_ALT3 | IBE | SRC | WPE;                //FEC_RX_CLK
  SIU.PCR[PCR249_FEC_RX_DV_PRIM].R       = PA_PRIM | IBE | WPE;                          //FEC_RX_DV
  SIU.PCR[PCR250_FEC_RXD0_PRIM].R          = PA_PRIM | IBE | SRC | WPE;              //FEC_RXD0
  SIU.PCR[PCR253_FEC_RXD1_PRIM].R          = PA_PRIM | IBE | SRC | WPE;              //FEC_RXD1
  SIU.PCR[PCR101_FEC_RXD2_ALT3].R           = PA_ALT3 | IBE | SRC | WPE;              //FEC_RXD2
  SIU.PCR[PCR107_FEC_RXD3_ALT3].R           = PA_ALT3 | IBE | SRC | WPE;              //FEC_RXD3

  //Input Multiplexing Register0(SIU_IMUX0) setting for FEC input pins
  SIU.IMUX0.R = IMUX0_MUXSEL6_FEC_TXCLK | IMUX0_MUXSEL1_FEC_RXDV | IMUX0_MUXSEL2_FEC_RXD0 | \
                   IMUX0_MUXSEL5_FEC_RXD1 | IMUX0_MUXSEL11_FEC_RXD2 | IMUX0_MUXSEL8_FEC_RXD3;

}

2. Could you explain more details about FEC clock setting? (MII-Lite interface)

 - I couldn't find any guideline to set FEC clock. Can you list up what register are needed to set and how they work?

 - Please check 'peripheral clock setting' below

#define SIU_SYSDIV_PERCLKSEL_NON_FM_CLOCK    0x1000000
#define SIU_SYSDIV_PERDIV_DIVIDE_BY_2                   0x0000000

...

//Peripheral Clock Setting, 50MHz / 2 => 25 MHz(Internal bus clock)
SIU.SYSDIV.R = SIU_SYSDIV_PERCLKSEL_NON_FM_CLOCK | SIU_SYSDIV_PERDIV_DIVIDE_BY_2;

...

FEC.MSCR.B.MII_SPEED = 0x5;       // 25MHz x  (1 / ( 5 x 2 )) = 2.5MHz

Thank you.

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taekyoungkim
Contributor II

I have checked that FEC was enabled and Ethernet packet was sent.

Thank you for the support.

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