Question aobut a Flash ECC module on MPC5674F

[youngseolee]

Last month, i have implemented a flash ECC error injection code with your help.

I have a question about a parity generation in the attached code.

================================================================================

/* step2. program data */
DFLASH_0.MCR.B.PGM = 1; // select operation (program)
*((unsigned int*) DATA_FLASH_addr_0) = 0x00450000; // first write
DFLASH_0.MCR.B.EHV = 1; // start the program operation
while(DFLASH_0.MCR.B.DONE == 0){}; // wait for DONE
DFLASH_0.MCR.B.EHV = 0; // operation end
*((unsigned int*) DATA_FLASH_addr_1) = 0x00000000; // additional write
DFLASH_0.MCR.B.EHV = 1; // start the program operation
while(DFLASH_0.MCR.B.DONE == 0){}; // wait for DONE
DFLASH_0.MCR.B.EHV = 0; // operation end
DFLASH_0.MCR.B.PGM = 0; // deselect operation

/* step3. over-program data - this generates ECC error */
DFLASH_0.MCR.B.PGM = 1; // select operation (program)
*((unsigned int*) DATA_FLASH_addr_0) = 0x00580000; // first write
DFLASH_0.MCR.B.EHV = 1; // start the program operation
while(DFLASH_0.MCR.B.DONE == 0){}; // wait for DONE
DFLASH_0.MCR.B.EHV = 0; // operation end
*((unsigned int*) DATA_FLASH_addr_1) = 0x00000000; // additional write
DFLASH_0.MCR.B.EHV = 1; // start the program operation
while(DFLASH_0.MCR.B.DONE == 0){}; // wait for DONE
DFLASH_0.MCR.B.EHV = 0; // operation end
DFLASH_0.MCR.B.PGM = 0; // deselect operation

================================================================================

In the step 2 code, parity bits is generated when the data is stored in the flash.

however, in the step 3 code, parity bits is not generated whe the data is stored in the flash.

I had understood that .

I had been understood parity bits is generated every time any data is written in the flash memory. 

is this wrong to do understand?

is there required some procedures for re-generation the parity bits? 

[romainm]

Hello,

Sorry for bringing this topic back to life but I've got an ecc generation code that doesn't work on a MCP5676R. I have followed my Reference Manual and the 

MPC5675K-2b_RAM+2b_FLASH_ECC_error_injection CW210 example without success. 

Here is the code I am using to try generate the ecc errror:

#include <F_MPC567xR.h>			/* Flash register manipulation */

#pragma ghs section rodata=".flash_section"
static const vuint32_t FLASH_test[] = 
{
    0xAAAAAAAA,
    0xBBBBBBBB,
    0xCCCCCCCC,
    0xDDDDDDDD
};
vuint32_t FLASH_test_read;

static vuint32_t data_to_be_written[] = 
{
    0x00450000, 0x00000000,
    0x00580000, 0x00000000   
};

const vuint32_t *p_FLASH_test = &FLASH_test[0];

static void generate_ecc_error()
{
    FLASH_A.LMLR.R = 0xA1A11111; // password, LME 0 -> 1 = unlocked.
    FLASH_A.LMLR.R = 0x3FD; // unlock L1 bock: L9(11 1111 1101)L0
	
    // /* step1. erase L1 (0x4000-0x7FFF) Note: This step looks good */
    FLASH_A.MCR.B.ERS = 1;
    FLASH_A.LMSR.B.LSEL = 0x002; // select L1 block L9(00 0000 0010)L0 = 0x2
    *((unsigned int*) p_FLASH_test) = 0xFFFFFFFF;  // interlock write 
    FLASH_A.MCR.B.EHV = 1; // start the erase operation
    while(FLASH_A.MCR.B.DONE == 0){}; // wait for DONE
    FLASH_A.MCR.B.EHV = 0;
    FLASH_A.MCR.B.ERS = 0;

	// /* step2. program data */
    FLASH_A.MCR.B.PGM = 1;
    *((unsigned int*) p_FLASH_test++) = data_to_be_written[0]; // first write
    *((unsigned int*) p_FLASH_test++) = data_to_be_written[1]; // additional write
    FLASH_A.MCR.B.EHV = 1;                                //start the erase operation
    while(FLASH_A.MCR.B.DONE == 0){}; //wait for DONE
    FLASH_A.MCR.B.EHV = 0;
    FLASH_A.MCR.B.PGM = 0;

	/* step3. over-program data - this generates ECC error */
    FLASH_A.MCR.B.PGM = 1;              
    *((unsigned int*) p_FLASH_test++) = data_to_be_written[2]; // first write
    *((unsigned int*) p_FLASH_test++) = data_to_be_written[3]; // additional write
    FLASH_A.MCR.B.EHV = 1;                                //start the erase operation
    while(FLASH_A.MCR.B.DONE == 0){}; //wait for DONE
    FLASH_A.MCR.B.EHV = 0;
    FLASH_A.MCR.B.PGM = 0;
    
    /* now here the ECC is checked and non-correctable error found */
    FLASH_test_read = FLASH_test[0];  // error caused by read
    FLASH_test_read = FLASH_test[1];
}

The ".flash_section" a 16KB section at address 0x6000 which is part of the FLASH_A's L1 block. After the step 1 the memory is erased properly, but step 2 and 3 don't reprogram the memory.

Any Idea ? 

[davidtosenovjan]

Hi, I suppose you mean ECC checksum bits (parity is something little bit different).

Are you asking why step 3 generates ECC error, right? It is just because erase operation is not executed before programming.

If you perform two consecutive program operation without erasing, the result will be its logic AND (of both, data and checksum). And for most of patterns after such operation stored checksum does not fit to expected checksum for stored data => ECC error

[youngseolee]

Hi, David

I am testing about the flash ECC error injection, and monitoring changes the storage data in the target flash memory(0x00EFC008 ~ 0x00EF00C).

I have tested following two conditions. 

======================================================================================

1. the original data value = 0xFFFFFFFF00000000, the over program data value = 0xFFFFFFFF00000001

2. the original data value = 0xFFFFFFFF00000001, the over program data value = 0xFFFFFFFF00000000

======================================================================================

In the first condition, the data stored in the target flash memory(0x00EFC008 ~ 0x00EF00C) is changed when i try to over program in the target flash memory. 

But, in the second condition, the data stored in the target flash memory is not changed when i try to over program in the target flash memory. 

Both of these condition, the flash ECC error interrupt is generated when i try to read the target memory location. 

Is it related to the logic you said?

Is this second test result (the over program data is not written in the target flash memory) related to the "logic AND" you said?

could you explain about a over program sequence in flash memory in detail?

[davidtosenovjan]

Single bit ECC error reporting must be also enabled in UT0[SCBE]. Following sequence must be used for that:
/* 1. Enable UTest mode */
CFLASH.UT0.R = 0xF9F99999;
/* 2. Enable single bit error correction */
CFLASH.UT0.B.SBCE = 1;
/* 3. Finish the UTest mode by writing UT0[UTE] with 0. */
CFLASH.UT0.B.UTE = 0;

[youngseolee]

Thank you for your answer, but I can not understand the checksum generation logic.

Please answer about two additional questions. 

1. Can you tell me what the sentence ' the result will be its logic AND' means?

Does this meaning that a result of the AND calculation of a stored data and a over program data  is stored when i perform over programming the data in the flash memory without erasing?

Can you explain in detail about the operation of Flash data writing and checksum generation?

2. Is it correct that the correction of the data is performed in the flash write operation, and the ECC error report interrupt occurs in the memory read operation?

I'll wait for your answer.

thank you.