Hi, I am using DEVKIT-MPC5744P. I set clock configuration according to AN5393 clock calculator guide that refer to excel file. Clocks are set to max and system clock set to 200 MHz. When I calculate the sys clc via logic analyzer I observed that system clock is 10 MHz. I examined the code register level generated by calculator but I did not find any mistake. I shared clock init and init perip clock gen. below. How can I set the sys clc(main clock) to 200 MHz. Can you help me at this point? Thanks for your interesting.
//Enable XOSC, PLL0, PLL1, and enter RUN0 with PLL1_PHI as system clock (200 MHz).
void SysClk_Init(void)
{
MC_CGM.AC3_SC.R = 0x01000000; //Connect XOSC to the PLL0 input.
MC_CGM.AC4_SC.R = 0x03000000; //Connect PLL0_PHI1 to the PLL1 input.
//Set PLL0 to 160 MHz with 40 MHz XOSC reference.
PLLDIG.PLL0DV.R = 0x40024020; //PREDIV = 4, MFD = 32, RFDPHI = 2, RFDPHI1 = 8
MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,XOSCON,PLL0ON,syclk=IRC
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
//Set PLL1 to 200 MHz with 40 MHz PLL0_PHI1 input.
PLLDIG.PLL1DV.R = 0x00020014; //MFD = 20, RFDPHI = 2
PLLDIG.PLL1FD.R = 0x00000000; //EnableandconfigurationfractionalmultiplierforPLL1
MC_ME.RUN_PC[0].R = 0x000000FE; //Enable peripherals to run in all modes
MC_ME.RUN0_MC.R = 0x001300F4; // RUN0 cfg: IRCON, XOSCON, PLL0ON, PLL1ON, syclk=PLL1_PHI
MC_CGM.SC_DC0.R = 0x80090000; //Divide system clock by 10 to achieve PBRIDGEx_CLK of 20 MHz
// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
}
void InitPeriClkGen(void)
{
MC_CGM.SC_DC0.R = 0x80090000; //PBRIDGEx_CLK at system clock divided by 10 (20 MHz).
MC_CGM.AC0_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 0.
MC_CGM.AC0_DC0.R = 0x800F0000; //MOTC_CLK: Enabled at Auxiliary Clock 0 divide by 16(10 MHz).
MC_CGM.AC0_DC1.R = 0x80070000; //SGEN_CLK: Enabled at Auxiliary Clock 0 divide by 8(20 MHz).
MC_CGM.AC0_DC2.R = 0x80010000; //ADC_CLK: Enabled at Auxiliary Clock 0 divide by 2(80 MHz).
/* Auxiliary Clock 1 is always sourced from PLL0_PHI. */
MC_CGM.AC1_DC0.R = 0x80010000; //FRAY_CLK: Enabled at Auxiliary Clock 1 divided by 2 (40 MHz).
MC_CGM.AC1_DC1.R = 0x80010000; //SENT_CLK: Enabled at Auxiliary Clock 1 divided by 2 (80 MHz).
/* Auxiliary Clock 2 is always sourced from PLL0_PHI. */
MC_CGM.AC2_DC0.R = 0x80010000; //CAN_CLK: Enabled at Auxiliary Clock 2 divided by 2 (40 MHz).
MC_CGM.AC5_SC.R = 0x02000000; //Select PLL0_PHI as source of Auxiliary Clock 5.
MC_CGM.AC5_DC0.R = 0x80070000; //LFAST_PLL: Enabled at Auxiliary Clock 5 divided by 8 (20 MHz).
MC_CGM.AC6_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 6.
MC_CGM.AC6_DC0.R = 0x80000000; //CLKOUT0: Enabled at Auxiliary Clock 6 divided by 1 (200 MHz).
MC_CGM.AC10_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 10.
MC_CGM.AC10_DC0.R = 0x80030000; //ENET_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).
MC_CGM.AC11_SC.R = 0x04000000; //Select PLL1_PHI as source of Auxiliary Clock 11.
MC_CGM.AC11_DC0.R = 0x80030000; //ENET_TIME_CLK: Enabled at Auxiliary Clock 10 divided by 4 (50 MHz).
}
