Hi,
both cores can access whole memory map, so data can be simply shared in RAM memory. You can allocate required amount of RAM in the linker file. If cache memory is enabled on e200z6 core, make sure that shared area is configured in MMU as cache inhibited to ensure data coherency.
It is also possible to use semaphores to ensure data coherency on application level (i.e. before a core can update or read memory coherently, it has to check the semaphore to see if other core is not already updating the memory).
It is also possible to use software interrupt to inform other core that required data are already present in shared memory.
Posix Message Queues - this is just software implementation. It depends which software (OS) you use...
Regards
Lukas
