PHY_Read is always returning 0xFFFF (MCU: MPC5775B, PHY: KSZ8061RNB)

[DivyaVyas]

Hello,

I am developing Ethernet communication using MPC5775B.
ENET and PHY modules are incorporated. PHY used is KSZ8061RNB and the PHY type chosen is Phy Generic.
RMII Mode is chosen. Auto negotiation and AutoMDIx configurations are enabled.
Pin strapping Config: 111 (RMII Normal Mode and AutoMDIx)
During run time, I verified all the FEC registers and PHY registers.
I could find the FEC_EIMR, ECR, MSCR, MMFR, TCR and RCR Register values proper, and all intended configurations are reflected in the internal registers,
except that the PHY_Read is always returning 0xFFFF.

Steps taken to troubleshoot:
The power supply is stable. VDDIO and RefClk are stable. No FEC Error flags are set.
1. Checked if the system is stuck in reset state. ECR register is telling that the reset is asserted, acknowledged and deasserted successfully on FEC.
Probed on Reset pin of PHY and confirmed that it's released and stable before read attempt.
2. Checked the Phy Address configuration. It is configured to be 0x01 via HW Pin strapping and also in Software. This is getting reflected in MMFR Register.
3. A pull down is given on RXD0 for enabling auto negotiation.
4. Checked the pull up on MDIO line (1K pullup).
5. Tried reducing the MDC frequency from 2.5MHz to 1MHz.
6. Probed on MDC line and confirmed that the clock is stable.
7. Checked the MII Field of MSCR Register and the MII speed is proper (49d or 31h with FEC0_Clk as 100MHz, when MDC frequency is 1MHz) (19d or 13h with FEC0_Clk as 100MHz, when MDC frequency is 2.5MHz).
8. Scanned all Phy addresses (0x00 to 0x1F). All are returning 0xFFFF.
9. Probed on MDIO line and checked the activity while read and write operation, keeping a GPIO as trigger.
10. The MDIO activity is verified via serial monitor logs.

Observation:
Please find the FEC Register values below.
FEC Error Flags: 0x00000000
EIMR Register: 0x6A780000
MSCR Register: 0x00000026
MMFR Register: 0x6083FFFF
ECR Register: 0xF0000002
TCR Register: 0x00000004
RCR Register: 0x05EE012C

The opmode, start frame delimiter, register address and phy address fields of MMFR are proper.
However, there is no low pulse on MDIO in the Turn Around + Data phase.
That means PHY is not acknowledging MDIO read.
As per my understanding, the FEC module handles the turnaround and data driving portions of MDIO reads internally.

I have attached the Observation on CRO, herewith.
Please check and let me know what change is required to get the PHY respond with proper TA and Data phase.

Thanks, and Kind Regards,
Divya

[PetrS]

Hi,

the SMI signals looks correct. The TA field is 2 bits long. When data is being written to the PHY, the MAC writes '10' to the MDIO line. When data is being read, the MAC releases the MDIO line at first bit and PHY put  '0' on second bit. So as you wrote this seems to be PHY issue.
From scope pictures I see RST is still asserted. Is there reset deassertion before PHY access? The strap-in pins are latched at the deassertion of reset.

BR, Petr

[DivyaVyas]

Hello Petr,

Thanks a lot for the reply.

The trigger signal shown in the diagram is a GPIO signal configured to track the timestamp of first read operation. The Digital signal is cleared before writing into base->MMFR, inside ENET_WriteManagementFrame(). It is set after completion. I had captured PHY Reset signal separately. I could find that the reset signal is deasserted before the read activity on MDIO. I had checked the ECR register and confirmed that the ENET reset is also asserted and deasserted successfully during initialization. 

Read operation is always returning 0xffff. But write operation is successful.

As you said, I shall check PHY for MMFR TA field.

Please let me know if there are any further points to be cross verified.

Thanks, and Kind Regards,

Divya

[PetrS]

Hi,

how is the MDIO pin configured. There should be OBE and IBE bit set. The voltage level looks weird little bit for zero level. What is your SMI circuitry?

BR, Petr

[DivyaVyas]

Hello Petr,

Thanks, a lot for the reply.

Please find the configuration below.

OBE and IBE are enabled for MDIO pin.

To capture both read and write operations distinctly using GPIO trigger signal, it is 
conditionally toggled based on the opType, while keeping the same timing — before writing to MMFR, and after the operation is complete. 

Observation on CRO: 

I could find high impedance state upon TA first bit (3.2V), during read operation. However, the second bit is not 0 (Problematic).

During write operation, TA bit field is loaded with '10', which is proper.

I am checking the PHY. Please provide suggestions.

Thanks, and Kind Regards,

Divya

[PetrS]

Hi,

I have nothing more to add. This seems to be PHY issue.
You can try to disconnect PHY and measure lines for SMI read/write, just to see signals generated by MCU, but ensure pullup is connected.

BR, Petr