Offline BIST returning fails on MPC5744P

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Offline BIST returning fails on MPC5744P

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igormodino
Contributor III

Hi all.

I'm creating a small driver for BIST for the MPC5744P in order to enable/disable it and get relevant information (LBIST/MBIST completion status and result, ...) and I'm finding that LBIST status register is always returning 0b11, meaning that tests on partitions 2 and 3 failed.

While tracing it I got 0b1111 in some cases but can not reproduce it consistently. I've found a note about executing LBIST in the Flash can leave it in an unknown state and I'm not sure if that can be the case (http://www.nxp.com/docs/en/errata/MPC5744P_1N65H.pdf).

I'm just using offline BIST (which is enabled by default). All other registers are OK (STCU status, MBIST status and completion and LBIST completion).

Does anyone have any idea what can be going on and how to get more information around it?.

Thanks.

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17 Replies

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VladiKn
Contributor III

Hello everybody,

It's been a while since this post was active but this is the only post I found on this topic.
I am using the MPC5744P development kit and I have the same issue with offline BIST. It gives the same result, LBIST partitions 2 and 3 failed and when I check the status register I see that the NCSFS bit is set.
Has anybody been able to solve this issue?

Cheers,
Vladimir

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

Ok as I said only what comes to my mind is power supply or external events.

Maybe your STCU BIST watchdog timeout is not sufficient enough for your setup.

I do not know which kind of debugger are you using, but I can prepare for you Lauterbach script.

Or tell me if you are able to load DCF records via your tool.

I can prepare DCF record for STCU watchdog with extended timeout.

Peter

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igormodino
Contributor III

Thanks Peter.

We are using S32 Design Studio and I'm doing the tests for programming the DCF records straight in code, writing to the flash.

We are debugging on S32 too, via JTAG. It would be great to know how to change the STCU watchdog.

Regards.

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petervlna
NXP TechSupport
NXP TechSupport

Ok,

Please try to add following DCF record on first available DCF record space in UTEST.

address: 0x00000318 - adjust it according your DCF flash area

data: 0xFFFFFFFF00080014         ;STCU_WDG max timeout

I know this is not recommended configuration but I hope we can see all tests pass.

Peter

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igormodino
Contributor III

Thanks you very much, Peter.

I've added the suggested register in the first free DCF record but the result is still the same. For reference, my DCF records look like this:

Base DCF address: 0x00400200

Content: 05AA55AF 00000000 55AA55AA 0100000C 00000301 00080000 FFFFFFFF 00080014 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF

In bold italic the new register

Thanks again for the support.

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igormodino
Contributor III

Dear Peter.

Any further update on this?

Thanks!

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

Actually your UTEST DCF records looks OK.

ERR_STAT is clear in your case. Only thing which comes to my mind is external event, like weak power supply, EMC, etc...

Do you still have this issue?

Peter

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igormodino
Contributor III

Dear Peter.

Unfortunatelly, yes, we are still having the same issues :smileysad:

Best regards,

Igor

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petervlna
NXP TechSupport
NXP TechSupport

Ok,

I will attach here my STCU configuration for offline BIST so you can compare it to yours and check if STCU is configured correctly.

Let me know if you find any difference.

Peter

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igormodino
Contributor III

Thanks Peter.

I've checked some of the registers and the value son my side are the same you reported. Checked registers are:

STCU.CFG;
STCU.ERR_STAT;
STCU.WDG;
STCU.LBS;
STCU.LBE;
STCU.LB[0].CTRL;
STCU.LB[0].PCS;
STCU.LB[1].CTRL;
STCU.LB[1].PCS;
STCU.LB[2].CTRL;
STCU.LB[2].PCS;
STCU.LB[3].CTRL;
STCU.LB[3].PCS;

Correct me if I'm wrong, but from what I understand from the reference manual, there's no configuration needed for offline BIST other than writing the right DCF record, which is actually pre-programmed from the factory (I've checked and it's there :smileygrin:).

What are the factors, other than real errors, that can affect LBIST result?; pin configuration/multiplexing?; clock configuration?... Sorry, but there's quite little explanation in the documentation about BIST and it's my first time working with it, so I must be missing something obvious.

Thanks!

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petervlna
NXP TechSupport
NXP TechSupport

Ok,

I wanted to see only if your DCF records (factory programmed) are correct.

We provide little information because customers like to play with BIST configuration and then they run into problems.

The mechanism itself is quite complicated.

Do you use NXP evaluation board or your own designed board?

Peter

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igormodino
Contributor III

Thanks Peter.

At the moment I have 3 board in my desk: an NXP (Freescale marked actually) dev board and 2 of our custom boards. With one of them I played a bit just to try and disable the BIST and enable it again. Most likely this will never be used but wanted to make sure we can do it. The other board hasn't been modified "BIST wise", so is used for reference.

When disabling BIST, whenever I check the LBIST or MBIST completion register, it's always not finished, which I guess is the sign of BIST not being performed. When the DCF record to activate BIST is set again, I check the completion register for LBIST and MBIST and both report all test as finished, as expected, but as said, results in LBIST are not all OK.

Following is a capture of the Flash on the eval board:

DevBoard.png

The same capture from our custom board used for reference (no BIST modified):

CleanVCU.png

Last the same capture from our custom board used to test (BIST records have been modified several times):

DirtyVCU.png

Please keep in mind none of the boards report all LBIST tests as successful: dev board reports a problem on LBIST0 and the other 2 on LBIST2 and LBIST3. The firmware in all of them is the same.

I'm using S32 Design Studio and for reading the LBIST result I'm using this define found on MPC5744P.h file (automatically added when creating the project), version 6.0.0:

#define STCU_LBS STCU.LBS.R /* STCU2 Startup LBIST Status Register */

Thanks.

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

This is strange as I have used EVB and just put fresh chip inside.

Whole BIST was successful with 0 errors.

I would expect some issues on your custom board but not on the EVB.

Can you see errors in ERR_STAT register?

Peter

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igormodino
Contributor III

Hi Peter.

On the EVB the ERR_STAT is clear and only LBIST_0 is 0; the rest is 1.

Thanks.

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petervlna
NXP TechSupport
NXP TechSupport

Hi,

I just tested it on cut 1N15P. You can see my results below:

pastedImage_1.png

e8128: LBIST: LBIST of the flash may leave flash in an unknown state and stress flash bit cells

It occurs only if device is reset while LBIST is executing flash array registers check. So I expect this is not your case.

Did you see LBIST fail on multiple devices?

Peter

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igormodino
Contributor III

Thanks Peter.

I've tried in 2 units of our board and are having the same result. The NCFSF bit of STCU error register is set to 1, which I assume is OK due to the LBIST failing.

In theory there's no configuration needed for the offline BIST as it's enabled by default and the results can be read at any time; is this right?

I'll try with a Freescale development board to see if I get any different result.

Thanks.

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igormodino
Contributor III

Using a development board the LBIST marks an error at partition 0, MBIST is ok and STCU error is all clear.

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