Hi,
The "ON DIE TERMINATE" bit (DDR_SYS_CONFIG register) controls on-die termination (ODT) in the controller. If this bit is 1, the internal pads generate ODT during read. If the bit is 0, no ODT is provided.
The MPC5125 always generates MODT signal. It generates MODT signal if "ON DIE TERMINATE" bit is cleared or set.
The ODT in the DRAM is controlled via the DRAM internal configuration registers. Please consult DRAM data sheet for more references.
Regarding drive strength, please refer to MPC5121ERM Table 22-2. IO_CONTROL_MEM Field Descriptions
https://www.nxp.com/docs/en/reference-manual/MPC5121ERM.pdf
CONT_DS and DATA_DS fields can be used to control the strength.
Actual settings and the resulting drive currents are described in MPC5121EDS Table 7
https://www.nxp.com/docs/en/data-sheet/MPC5121E.pdf
Use configuration 0b110 to define DDR2 full strength and 0b010 for DDR2 half strength.
Regards,
Lukas
