Hi,
I´m using the DEVKIT-MPC5748G and DEVKIT-COMM to develop a CAN gateway. I need to use 5 FlexCANs. Everything is working with FlexCAN_0, 1 and 3 but FlexCAN_5 and 7 will not work. Forced to used those FlexCANs due to they are available on the DEVKITs. Project compiles and uploads ok to the board but when I´m trying to send messages to the board I get error frames on FlexCAN_5 and 7, but FlexCAN_0, 1 and 3 is ok. This is my code:
FlexCAN_0 that is working
/********************************************************************************/
/* Initialize FlexCAN_0 GWCAN0 */
/********************************************************************************/
void FlexCAN_0_init(void)
{
/* Int used in for-loops */
int i = 0;
/* Set IRQ for FlexCAN_0 RX */
//INTC.PSR[568].R = 0xF; //set interrupt core and priority
/* Configure GPIO for FlexCAN_0 */
SIUL2.MSCR[16].B.SSS = 1; /* Pad PB0: Source signal is CAN0_TX */
SIUL2.MSCR[16].B.OBE = 1; /* Pad PB0: Output Buffer Enable */
SIUL2.MSCR[16].B.SRC = 3; /* Pad PB0: Maximum slew rate */
SIUL2.MSCR[17].B.IBE = 1; /* Pad PB1: Enable pad for input - CAN0_RXD */
SIUL2.IMCR[188].B.SSS = 2; // CAN0_RX: connected to pad PB1 ** FUNKAR!! ***
/* Configure FlexCAN_0 module */
CAN_0.MCR.B.MDIS = 1; // Disable module before selecting clock source
CAN_0.CTRL1.B.CLKSRC = 0; // Clock source is oscillator clock (40MHz)
CAN_0.MCR.B.MDIS = 0; // Enable module for configuration (Sets FRZ, HALT)
while (!CAN_0.MCR.B.FRZACK) {} // Wait for freeze acknowledge to set
CAN_0.CTRL1.R = SetCTRL1(); // CAN bit timing
CAN_0.RXFGMASK.R = 0; // Global acceptance mask FIFO 0 = Accept all
/* Clear all RX individual Mask Registers */
for(i = 0; i < 96; i++) { CAN_0.RXIMR[i].R = 0; }
CAN_0.IFLAG1.R = 0xFFFFFFFF; // Clear all RX flags
/* Leave freeze mode and start module with 32 MBs */
CAN_0.MCR.R = SetMCR(); // Enable module with settings
while (CAN_0.MCR.B.FRZACK & CAN_0.MCR.B.NOTRDY) {} /* Wait to clear */
}
FlexCAN_5 that is not working
/********************************************************************************/
/* Initialize FlexCAN_5 GWCAN5 */
/********************************************************************************/
void FlexCAN_5_init(void)
{
/* Int used in for-loops */
int i = 0;
/* Set IRQ for FlexCAN_5 RX */
//INTC.PSR[628].R = 0xF; //set interrupt core and priority
/* Configure GPIO for FlexCAN_5 */
SIUL2.MSCR[65].B.SSS = 1; /* Pad PE1: Source signal is CAN5_TX */
SIUL2.MSCR[65].B.OBE = 1; /* Pad PE1: Output Buffer Enable */
SIUL2.MSCR[65].B.SRC = 3; /* Pad PE1: Maximum slew rate */
SIUL2.MSCR[64].B.IBE = 1; /* Pad PE0: Enable pad for input - CAN5_RXD */
SIUL2.IMCR[193].B.SSS = 1; /* CAN5_RX: connected to pad PE0 */
/* Configure FlexCAN_5 module */
CAN_5.MCR.B.MDIS = 1; // Disable module before selecting clock source
CAN_5.CTRL1.B.CLKSRC = 0; // Clock source is oscillator clock (40MHz)
CAN_5.MCR.B.MDIS = 0; // Enable module for configuration (Sets FRZ, HALT)
while (!CAN_5.MCR.B.FRZACK) {} // Wait for freeze acknowledge to set
CAN_5.CTRL1.R = SetCTRL1(); // CAN bit timing
CAN_5.RXFGMASK.R = 0; // Global acceptance mask FIFO 0 = Accept all
/* Clear all RX individual Mask Registers */
for(i = 0; i < 96; i++) { CAN_5.RXIMR[i].R = 0; }
CAN_5.IFLAG1.R = 0xFFFFFFFF; // Clear all RX flags
/* Leave freeze mode and start module with 32 MBs */
CAN_5.MCR.R = SetMCR(); // Enable module with settings
while (CAN_5.MCR.B.FRZACK & CAN_5.MCR.B.NOTRDY) {} /* Wait to clear */
}
Return of SetCTRL1(); is 0x09DB0086
250 kbps
Return of SetMCR(); is 0x2002000C
FIFO enabled, SRXDIS enabled, 12 mailboxes
As you can see the settings are the same. I have checked and double checked the SIUL2 settings and aslo consluted the RM attached XLS sheet to see that the IMCR SSS is correct.
DEVKIT-MPC5748G is rev B and DEVKIT-COMM is rev A.
I´m using S32DS for Power Architecture 2017.R1 build 171018
Thankfull for help!
Best regards, Joakim