Mcan transmit

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Mcan transmit

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Saidev
Contributor II

Hi,

Currently I'm working on MPC5777c custom board. Here I'm facing a issue in programming MCAN_0.

I referred given examples in community which is for GHS, however I'm using S32_DS

IDE. So far I altered the program for S32_ds in project M_CAN Simple Tx/Rx.

I uploaded the program I used and I want to know is there any mistake I made in ASM program or in main.

#include "Cpu.h"

  volatile int exit_code = 0;
/* User includes (#include below this line is not maintained by Processor Expert) */
#include "MPC5777C.h"
#include "stdio.h"

uint8_t MCAN_0_data[8]={'.','.','.','H','e','l','l','o'};

#define MCAN0_BASE_ADDR		0xFFE30000
#define MCAN_MSG_RAM_LENGTH 	0x4000

#define MCAN_MSG_RAM_BASE_ADDR 	0xFFE34000
#define MCAN_MSG_RAM_LENGTH 	0x4000

#define MCAN0_SIDFC_FLSSA 0x0000   	//STANDARD MESSAGE ID FILTERS
#define MCAN0_XIDFC_FLESA 0x0200   	//EXTENDED MESSAGE ID FILTERS
#define MCAN0_RXF0C_F0SA 0x0400    	//RXFIFO 0 ELEMENTS
#define MCAN0_RXF1C_F1SA 0x0800	//RXFIFO 1 ELEMEMNTS
#define MCAN0_RXF1S_DMS 0x0BF4
#define MCAN0_TXEFC_EFSA 0x0C00    	//TX Event FIFO
#define MCAN0_TXBC_TBSA 0x0000     	//TXBUFFER ELEMENTS

#define WRITE_MSG_RAM(offset, data) *(uint32_t *)(MCAN_MSG_RAM_BASE_ADDR + offset) = data
#define READ_MSG_RAM(offset) *(vuint32_t*)(MCAN_MSG_RAM_BASE_ADDR + offset)
#define READ_MSG_RAM_8bit(offset) *(vuint8_t*)(MCAN_MSG_RAM_BASE_ADDR + offset)


void delay(volatile uint8_t x)
{
	while(x--);
}

static void User_HW_init(void)
  {
      /* set round robin for all slaves */
      XBAR->PORT[0].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[1].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[2].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[3].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[4].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[6].CRS = XBAR_CRS_ARB(1);
      XBAR->PORT[7].CRS = XBAR_CRS_ARB(1);

  }

static void MCAN_MSG_RAM_Init(void)
{
    int i;
    uint32_t *pMsgRAM = (uint32_t*)MCAN_MSG_RAM_BASE_ADDR;

    for(i=0;i<MCAN_MSG_RAM_LENGTH/4;i++)
    {
	*pMsgRAM++ =  0x0;
    }
}


static void MCAN_0_Init(void)
{
    // put module to Init mode
    M_CAN_0->CCCR = M_CAN_CCCR_INIT(1);    //.B.INIT = 0x1;
    while(M_CAN_CCCR_INIT_MASK == 0)
    {
	asm("nop");
    }

    // enable CCE bit to change config
    M_CAN_0->CCCR =  M_CAN_CCCR_CCE(1);      //.B.CCE = 0x1;
    while(M_CAN_CCCR_CCE_MASK==0)
    {
	asm("nop");
    }

    M_CAN_0->CCCR &=  M_CAN_CCCR_FDOE(0);   //.B.CMR = 0x0;	//No CAN FD
    M_CAN_0->CCCR &= M_CAN_CCCR_BRSE(0);           //.B.CME = 0x0;

    M_CAN_0->DBTP =  0x00011E77;            //.BTP.R = 0x00011E77;  // Set time quanta for 0.5Mbps SYNC=1, TSEG1=30+1, TSEG2=7+1, SJW=7+1


    M_CAN_0->GFC = (0
	             | 3<<4	// Reject non-matching standard frames in Rx FIFO 0
		     | 3<<2	// Reject non-matching extended frames in Rx FIFO 1
		     | 1<<1	// Reject Remote Frames Standard
		     | 1);	// Reject Remote Frames Extended

    M_CAN_0->TXBC =  (0				// tx buffer
	               | 2 << 16		// space for 2 messages
		       | MCAN0_TXBC_TBSA); 	// starting at offset MCAN0_TXBC_TBSA

    M_CAN_0->RXESC = 0x00000000;	//set for 8 data bytes both RX FIFO 0 and FIFO 1
    M_CAN_0->TXESC = 0x00000000;	//set for 8 data bytes tx buffer




    M_CAN_0->CCCR &= M_CAN_CCCR_INIT(0);        //.B.CCE = 0x0;
    M_CAN_0->CCCR &= M_CAN_CCCR_CCE(0);          //.B.INIT = 0x0;				//re-enable CCCR protection
    //while((M_CAN_0->CCCR & 0x1)==1)
   // {

   // }


    /* configure MCAN0TX and MCAN0RX pin functions on PCR83 and PCR84 */
    SIU->PCR[83] = 0x0E0C; /* MCAN0TX, push/pull, max slew rate */
    SIU->PCR[84] = 0x0D03; /* MCAN0RX, weak pull device disabled */
    SIU->IMUX1 |= SIU_IMUX1_MUXSEL1(1) ;  // select MCANRX0 for PCR[84]

}

void MCAN_ID_init()
{

    //MCAN1 std ID table MCAN1_SIDFC_FLSSA
    WRITE_MSG_RAM( MCAN0_SIDFC_FLSSA,
	           0		// Standard Message ID filter element 1
	            | 0x2<<30	// Classic filter: SFID1 = filter (ID), SFID2 = mask
		    | 0x1<<27	// Store in Rx FIFO 0 if filter matches
	            | 0x123<<16	// ID = 0x123
		    | 0x7FF); 	// mask = 0x7FF


    WRITE_MSG_RAM( MCAN0_SIDFC_FLSSA + 0x04,
	           0		// Standard Message ID filter element 2
	            | 0x2<<30	// Classic filter: SFID1 = filter (ID), SFID2 = mask
		    | 0x1<<27	// Store in Rx FIFO 0 if filter matches
		    | 0x456<<16	// ID = 0x456
		    | 0x7FF); 	// mask = 0x7FF

    //MCAN1 ext ID table at offset MCAN1_XIDFC_FLESA
    WRITE_MSG_RAM( MCAN0_XIDFC_FLESA ,
	           0		// extended Message ID filter element 1, word F0
	            | 0x2<<29	// Store in Rx FIFO 1 if filter matches
		    | 0x123);	// ID = 0x123

    WRITE_MSG_RAM( MCAN0_XIDFC_FLESA  + 0x04,
	           0		// extended Message ID filter element 1, word F1
	            | 0x2<<30	// Classic filter: EFID1 = filter (ID), EFID2 = mask
		    | 0x1FFFFFFF);  // mask = 0x1FFFFFFF

    WRITE_MSG_RAM( MCAN0_XIDFC_FLESA  + 0x08,
	           0		// extended Message ID filter element 2, word F0
	            | 0x2<<29	// Store in Rx FIFO 1 if filter matches
		    | 0x456);	// ID = 0x123

    WRITE_MSG_RAM( MCAN0_XIDFC_FLESA  + 0x0C,
	           0		// extended Message ID filter element 2, word F1
	            | 0x2<<30	// Classic filter: EFID1 = filter (ID), EFID2 = mask
		    | 0x1FFFFFFF);  // mask = 0x1FFFFFFF
}


static void MCAN_0_TransmitMsg(uint8_t ext, uint32_t ID, uint8_t lenght)
{
    uint32_t txID;

    if (ext==0) txID = ID<<18;
    else txID = ID;

    if (M_CAN_0->TXBRP == 0)
    {

	int z;

	WRITE_MSG_RAM( MCAN0_TXBC_TBSA,
		       0		// Tx Buffer 0 T0 word
		        | ext<<30	// standard ID
			| 0<<29		// transmit data frame
			| txID); 	// message ID

	WRITE_MSG_RAM( MCAN0_TXBC_TBSA  + 4,
		       0		// Tx Buffer 0 T1 word
		        | 0<<23		// do not store TX event
			| (lenght << 16)); // dlc... data length

	for(z = 0; z < lenght; z+=4)	// fill rest of Tx Buffer 0 Tn words with data
	{
	    WRITE_MSG_RAM( MCAN0_TXBC_TBSA  + 8 + z, MCAN_0_data[z] | (MCAN_0_data[z+1]<<8) | (MCAN_0_data[z+2]<<16) | (MCAN_0_data[z+3]<<24));
	}

	M_CAN_0->TXBAR = 0x1;	// start transmission for M_CAN0 TX buffer 0
   }
}

/*! 
  \brief The main function for the project.
  \details The startup initialization sequence is the following:
 * - startup asm routine
 * - main()
*/
int main(void)
{
  /* Write your local variable definition here */
int i;
uint32_t freq;
  /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
  #ifdef PEX_RTOS_INIT
    PEX_RTOS_INIT();                   /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
  /*** End of Processor Expert internal initialization.                    ***/

  /* Write your code here */

    //CLOCK_SYS_Init(g_clockManConfigsArr, CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, CLOCK_MANAGER_CALLBACK_CNT);

           //CLOCK_SYS_UpdateConfiguration(0u, CLOCK_MANAGER_POLICY_AGREEMENT);
    CLOCK_DRV_GetFreq(MCAN0_CLK, &freq);

    CLOCK_DRV_Init(&g_clockManConfigsArr);

    PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, &g_pin_mux_InitConfigArr);

    MCAN_MSG_RAM_Init();

    MCAN_0_Init();

    MCAN_ID_init();


        for(;;)
        {
        	MCAN_0_TransmitMsg(0,0x123, 2);
        	delay(100);
        }
  /* For example: for(;;) { } */

  /*** Don't write any code pass this line, or it will be deleted during code generation. ***/
  /*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/
  #ifdef PEX_RTOS_START
    PEX_RTOS_START();                  /* Startup of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
  /*** End of RTOS startup code.  ***/
  /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/
  for(;;) {
    if(exit_code != 0) {
      break;
    }
  }
  return exit_code;
  /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/
} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

seems you have tx buffer elements and std id filters on the same RAM offset. This probably does not matter as you have no setting for RX things (id filters, rxfifo, rxmb) in MCAN init. Just TX buffers are enabled, so I think transmitting should work. Or do you see any issue?

But if you are using SDK, why you do not use SDK MCAN driver directly, there is mcan example for it too?

BR, Petr

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