MPC5777CRM EBI access by 2 cores

[Nagendra_Kumar]

Hi, I am trying to access EBI by 2 cores for accessing DPRAM(core 0) and for Flash and Ram(for core 1) and observed some data is being corrupted.

Kindly Help me in this regard.

Is this possible without using semaphores.

[davidtosenovjan · Accepted solution]

From hardware point of view it is possible.

You needed to have either disabled cache memories or enable cache snooping for all masters accessing this XBAR slave port (EBI). The same fro other slaves.

Maintaining software coherency is other topic and there using of semaphores is needed.

[Nagendra_Kumar]

Dear Sir,@davidtosenovjan

I found the following for achieving Memory Coherency,

For writes originating from either core, the MMU for the core must be configured with
Memory Coherence (M bit) and Write Through (W bit) set for the address spaces to be
accessed.

How to configure the MMU, Kindly Help

Awaiting your reply

[Nagendra_Kumar]

Hi @davidtosenovjan ,

Thanks for the reply, 

Could you please provide some example or some support code to disable cache memories or enabling the cache snooping of the slave . We have no idea how to do the same,

Thanks again