MPC5777C injection ecc ram error

[mauriziogreco]

Hi all

I would like introduce a unit test to check if ERM is able to get PRAMAC_0 uncorrectable errors.

I m using the EIM module but I found this kind of problem:

a) EIM is not able to inject a error only on one specific read access, so after having set EIM.EICHEN.R= 0x80000000

    and EIM,EIMCR.R=1 i think all access on RAM managed by PRAMAC_0 is "wrong".

b) The result of a) , from point of view of my set-up, is that also into IVOR exeception somethings is wrong and system will go into IVOR13 LOOP call (we are using MMU and we are working at lauterbach) 

I also tried to remove EIM.EIMCR.R enable with this :

.align 4
.globl EXCP_Iv12_Hnd
EXCP_Iv12_Hnd:
e_b exception_IVOR_12

.align 4
.globl EXCP_Iv13_Hnd
EXCP_Iv13_Hnd:
e_bl EIMCR_Reset
e_b exception_IVOR_13

.align 4
.globl EXCP_Iv14_Hnd
EXCP_Iv14_Hnd:
e_b exception_IVOR_14

.align 4
.globl EXCP_Iv15_Hnd
EXCP_Iv15_Hnd:
e_b exception_IVOR_15

I know that is not a real case! But I would like to have a test set-up where observe and trace what can do in a "possibile" fault reaction 

I think that EIM has introduced a general error on MMU managememt. How is it possibile insert Uncorrectable Errors into RAM but only into single location? 

I would like found a "similar" test condition how can be realized for testing ECC EDC flash using UTEST area!

Is possible?

Do you have a suggest?

Regards and thanks to all!

[davidtosenovjan]

Hi, that's just disadvantage of EIM module. It simply inverts specified data/checksum line on the internal data bus, but for all accesses upon injection enabling. It means the code must disable error injection before next access to area specified by EIM channel.
As double bit ECC error leads in machine check exception, its handler must disable error injection at the very beginning and the handler itself must be stored in different memory than the one where ECC error is injected into. It means in case ECC error is injected to the SRAM, exception handler needs to be located in FLASH or be locked in CACHE.
UTEST area may used for simulating of ECC/EDC error in FLASH.
On this device, for all internal RAM error injection, EIM module needs to be used.

Example code you may find here:
Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614 

For FLASH, you may also use flash over-programming:
Example MPC5777C-1b+2b_FLASH_ECC_error_injection GHS614 

ECC with using of UTEST I have preprared only for MPC5744P device (having MEMU instead of ERM):
https://community.nxp.com/docs/DOC-339955 

[fereyes08]

Hello,

I have a question regarding this topic. I am able to generate the fault in the ERM by reading the UTEST area.

I also have the following init:

// Enable EDC after ECC Error Detection
C55FMC.UT0.B.CPE = 1;

area *utest_ecc_flash = (uint32*)0x00400060;

But I cannot see the FAULT being propagated to the FCCU.

I would expect to see the FCCU status [45] [46].

Is this correct:

Do you have any suggestion?

Thanks

Federico

[davidtosenovjan]

It is needed to have these faults enabled in the FCCU.

Pay attention to following appnote to understand how to handle FCCU:

https://www.nxp.com/docs/en/application-note/AN5284.pdf 

[mauriziogreco]

Hi David. Thanks for your confirmation about this question.

I had already analyzed your ANxx document. I must say it was very useful to understand the particularities of the MPC5777C compared to other MPC5xx processors. I also already used your sample code as inspiration to implement some testing path.

Many Thanks.