MPC5777C eTPU channel interrupt generation

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MPC5777C eTPU channel interrupt generation

1,301 Views
prathapvc
Contributor III

Hi,

I am not able to generate eTPU channel interrupt for every 40ms when QOM loaded with counts corresponding to 40ms

Please refer the following settings done in

a) main.c

/* initialize pads */
SIU.PCR[ETPUB0_pin].R = (ALT1 | OBE | WPE | WPS | DRV) ;
SIU.PCR[ETPUB1_pin].R = (ALT1 | IBE | WPE | WPS | DRV) ;

ETPU.CIER_B.B.CIE0 = 0x1;
ETPU.CHAN[64].CR.R = 0x80000000; //enable interrupt

/* enable all timebases */
fs_timer_start ();

*upper_QOM_SCR16 = 0xC0C0; /* clear QOM DMA/interrupt service request */
*upper_FPM_SCR16 = 0xC0C0; /* clear FPM DMA/interrupt service request */

/* initialize eTPU channels */
// init QOM channel Low using QOM function
// init QOM channel Low using QOM function
error_code = fs_etpu_qom_init (QOM0,
FS_ETPU_PRIORITY_MIDDLE,
FS_ETPU_QOM_SINGLE_SHOT ,
FS_ETPU_TCR1,
FS_ETPU_QOM_INIT_PIN_LOW,
FS_ETPU_QOM_IMMEDIATE,
(uint32_t *) 0,
10,
QOMLO_array_size,
my_event_array_QOMA);//my_event_array_QOMLO

/* wait for QOM to finish */
while (ETPU.CHAN[QOM0].SCR.B.CIS == 0) {};

*upper_QOM_SCR16 = 0xC0C0; // clear DMA/interrupt service request

b) MPC5777C_IsrVecTab.c

IntcIsrVectorTable:

ISRline eTPU_B0_ISR ;Vec 243,

c) Interrupts.c

void Interrupts_init(void)
{
/* Initialize INTC for software vector mode */
INTC.MCR.R = 0x00000000;

/* configure IVPR and IVORx offsets, also includes a trap for all core
exceptions, excluding IVOR4 exceptions which have seperate handler */
e200zX_Interrupt_Setup();

/* Set INTC ISR vector table base address */
INTC.IACKR.R = (uint32_t) &IntcIsrVectorTable[0];
INTC.IACKR_PRC1.R = (uint32_t) &IntcIsrVectorTable[0];

/* assing required peripheral priorities */
INTC.PSR[244].R = PRC_SEL_CPU0 | PRC_PRI(1); // eTPU_B_chnl_1
/* assing required peripheral priorities */
INTC.PSR[243].R = PRC_SEL_CPU0 | PRC_PRI(1); // eTPU_B_chnl_0
}

7 Replies

983 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I am not sure what's the definition shown in your code

pastedImage_58.png

but in fact there two registers

eTPU_GCR_CIER_ENG1

eTPU_GCR_CIER_ENG2

in your case you need write the second one

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983 Views
prathapvc
Contributor III

Hi,

I have set the value to register eTPU_GCR_CIER_ENG2 through ETPU.CIER_B.B.CIE0 = 0x1 and we observed that when loaded QOM time has elapsed then ETPU.CHAN[QOM0].SCR.B.CIS is set to 1 (eTPU_GCR_CISR_ENG2[CIS0] = 1) but ISR mapped to this channel has not executed

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983 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Do you have enabled interrupts globally? Other interrupt sources works for you?

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983 Views
prathapvc
Contributor III

Hi David,

Possible can you share any example with eTPU ISR enabled.? 

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983 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

For instance you may see eTPU interrupt used in the code. It is working fine.

https://community.nxp.com/docs/DOC-335584 

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983 Views
prathapvc
Contributor III

I tried as per the  example code and its working now

Thank you

983 Views
prathapvc
Contributor III

Interrupts are enabled globally. Other interrupts like "Periodic Interrupt Timer Interrupt 0(Vector 301) and eSCI (vector 146) "are working in same workspace.  In ETPU after QOM executes ETPU.CHAN[QOM0].SCR.B.CIS this bit is set after given time elapsed but its not coming to ISR handler like PIT and eSCI.

 

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